Ney Calazans Publications (Sorted by Type)

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Journal Articles

Conference Papers

Books and Book Chapters

Advised or Presented Thesis (mostly in Portuguese)

Advised or Presented Dissertations (mostly in Portuguese)

Advised or Presented End of Term Works (mostly in Portuguese)

Advised or Presented Monographs (mostly in Portuguese)

Technical Reports and other Publications

Journal Articles

  1. CARARA, E. A., CALAZANS, N. L. V., MORAES, F. G. Differentiated Communication Services for NoC-Based MPSoCs. IEEE Transactions on Computers, 2012. Accepted for publication, in print.

  2. SOARES, R. I., CALAZANS, N. L. V., MORAES, F. G., MAURINE, P., TORRES, L. A Robust Architectural Approach for Cryptographic Algorithms using GALS Pipelines. IEEE Design & Test of Computers, 28(5), 2011. pp. 62-71.

  3. SOARES, R. I., CALAZANS, N. L. V., LOMNE, V., DEHBAOUI, A., MAURINE, P., TORRES, L. A GALS Pipeline DES Architecture to Increase Robustness against CPA and CEMA Attacks. JICS - Journal of Integrated Circuits and Systems, vol. 6, Mar. 2011, pp. 25-34.

  4. MARCON, C. A. M.; CALAZANS, N. L. V.; MORENO, E. I.; MORAES, F. G.; HESSEL, F. P.; SUSIN, A. A. CAFES: A Framework for Intrachip Application Modeling and Communication Architecture Design. Journal of Parallel and Distributed Computing vol. 71, 2011. pp. 714-728. 

  5. CARVALHO, Ewerson Luiz de Souza; CALAZANS, N. L. V.; MORAES, F. G. Dynamic Task Mapping for MPSoCs. IEEE Design & Test of Computers, 27(5), 2010. pp. 26-35.

  6. LOMNÉ, V., DEHBAOUI, A., ORDAS, Thomas, MAURINE, P., TORRES, Lionel, ROBERT, Michel, SOARES, Rafael Iankowski, CALAZANS, N. L. V., MORAES, F. G.  Secure Triple Track Logic Robustness against Differential Power and Electromagnetic Analyses. JICS - Journal of Integrated Circuits and Systems, vol. 4, no.1, 2009. pp. 20-28.

  7. MARCON, César Augusto Missio, MORENO, Edson Ifarraguirre, CALAZANS, Ney Laert Vilar, MORAES, Fernando Gehm. Comparison of NoC Mapping Algorithms Targeting Low Energy Consumption. IET Computers & Digital Techniques, vol. 2, no. 6. November, 2008. pp. 471-482. (ask for draft version by e-mail)

  8. TEDESCO, Leonel Pablo, CALAZANS, N. L. V., MORAES, F. G. Buffer Sizing for Multimedia Flows in Packet-Switching NoCs. JICS - Journal of Integrated Circuits and Systems. vol. 3, no. 1. March, 2008. pp. 146-156.

  9. CARARA, Everton Alceu, CALAZANS, N. L. V., MORAES, F. G. A New Router Architecture for High-Performance Intrachip Networks. JICS - Journal of Integrated Circuits and Systems. vol. 3, no. 1. March, 2008. pp. 123-131.

  10. MARCON, César Augusto Missio; PALMA, José Carlos Sant'anna; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Design and Prototyping of an SDH-E1 Mapper Soft-core. Revista da Sociedade Brasileira de Telecomunicações (currently called Journal of Communication and Information Systems - JCIS, Campinas, vol 20, no. 2, p. 74-82, August, 2005. 

  11. MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; OST, Luciano Copello. HERMES: an Infrastructure for Low Area Overhead Packet-switching Networks on Chip. Integration The VLSI Journal, Amsterdam, vol. 38, no. 1, p. 69-93, October, 2004. (ask for draft version by e-mail)

  12. PALMA, José Carlos Sant'anna; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Core Communication Interface for FPGAs. Journal Of Integrated Circuits And Systems, Porto Alegre, vol. 1, no. 1, p. 44-51, March 2004. (ask for draft version by e-mail)

  13. CAPPELATTI, Ewerton Artur, MORAES, F. G., CALAZANS, N. L. V., OLIVEIRA, Leandro Augusto de. Barramento de alto desempenho para interação software/hardware. Revista Tecnologia e Tendências. , v.3, p.7 - 18, 2004.

  14. MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MARCON, César Augusto Missio; MESQUITA, Daniel; PALMA, José Carlos Sant'anna; BLAUTH, Victor Hugo. Design and Prototyping of an E1 Drop_Insert Soft Cores. IEE Proceedings - Communications, London, vol. 150, no. 4, pp. 239-243, August, 2003. (ask for draft version by e-mail)

  15. CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Integrating the Teaching of Computer Organization and Architecture with Digital Hardware Design Early in Undergraduate Courses. IEEE Transactions on Education, Piscataway, vol. 44, no. 2, pp. 109-119, 2001. May, 2001. (ask for draft version by e-mail)

  16. CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; TOROK, Delfim Luiz; ANDREOLI, Andrey Vedana. Design for Prototyping of a MAC Ethernet IP soft Core. Revista de Informática Teórica e Aplicada, Porto Alegre, vol. 8, no. 1, pp. 23-41, 2001. (in Portuguese)

Conference Papers

  1. PONTES, J. J. H., CALAZANS, N. L. V., VIVET, P. Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects. In: 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'12), Lyngby, 2012. pp. 142-149.

  2. PONTES, J. J. H., CALAZANS, N. L. V., VIVET, P. An Accurate Single Event Upset Digital Design Flow for Reliable System Level Design. In: Design, Automation and Test in Europe, Dresden (DATE'12), 2012. pp. 224-229.

  3. PEREZ, T. D.; CALAZANS, N. L. V.; DE ROSE, C. A. F. A Preliminary Study on System-level Impact of Persistent Main Memory. In: International Symposium on Quality Electronic Design, Santa Clara (ISQED'12), 2012. pp. 85-90.

  4. MOREIRA, M. T.; OLIVEIRA, B. S.; PONTES, J. J. H.; MORAES, F. G.; CALAZANS, N. L. V. Impact of C-Elements in Asynchronous Circuits. In: International Symposium on Quality Electronic Design, Santa Clara (ISQED'12), 2012. pp. 438-444.

  5. HECK, G.; GUAZZELLI, R.; SOARES, R. I.; MORAES, F. G.; Calazans, N. L. V. HardNoC: A Platform to Validate Networks on Chip through FPGA Prototyping. In: VIII Southern Programmable Logic Conference (SPL'12), Bento Gonçalves, 2012, pp. 15 - 20.

  6. MOREIRA, M. T., OLIVEIRA, B. S., PONTES, J. J. H., MORAES, F. G., CALAZANS, N. L. V. Adapting a C-Element Design Flow for Low Power. In: IEEE International Conference on Electronics, Circuits, and Systems, Beirut (ICECS'11), 2011. pp 45-48.

  7. MOREIRA, M. T., OLIVEIRA, B. S., PONTES, J. J. H., CALAZANS, N. L. V. A 65nm Standard Cell Set and Flow Dedicated to Automated Asynchronous Circuits Design. In: 24th IEEE International SoC Conference (SoCC'11), 2011. pp. 99-104.

  8. ROSA, T.  R., GUINDANI, G., CARDOSO, D, CALAZANS, N. L. V.; MORAES, F. G. A Self-adaptable Distributed DFS Scheme for NoC-based MPSoCs. In: Symposium on Integrated Circuits and Systems Design (SBCCI'11), Sep. 2011. pp. 203-208.

  9. MORENO, E.; MARCON, C. A. M.; CALAZANS, N. L. V.; MORAES, F. G. Arbitration and Routing Impact on NoC Design. In: IEEE International Symposium on Rapid System Prototyping (RSP'11), Karlsruhe, May 2011. pp. 193-198.

  10. BENFICA, J., POEHLS, L. B., VARGAS, Fabian Luis, LIPOVETZKY, J., LUTENBERG, A., GARCÍA, S., GATTI, E., HERNANDEZ, F., CALAZANS, N. Configurable Platform for IC Combined Tests of Total-Ionizing Dose Radiation and Electromagnetic Immunity. In: IEEE Latin-American Test Workshop (LATW'11), March 2011.

  11. PONTES, Julian José Hilgemberg, MOREIRA, M. T., MORAES, F. G., CALAZANS, N. L. V. Hermes-AA - A 65nm Asynchronous NoC Router with Adaptive Routing. In: 23rd IEEE International SoC Conference (SOCC'10). IEEE Computer Society, Las Vegas, 2010. pp. 493-498.

  12. PONTES, J. J. H., MOREIRA, M. T., MORAES, F. G., CALAZANS, N. L. V. Hermes-A - An Asynchronous NoC Router with Distributed Routing. In: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'10), LNCS volume 6448, Grenoble, 2010. pp. 150-159.

  13. TEDESCO, L. P., ROSA, T. R. da, CALAZANS, N. L. V., CLERMIDY, F., MORAES, F. G. Implementation and Evaluation of a Congestion Aware Routing Algorithm for Networks-on-Chip. In: Symposium on Integrated Circuits and Systems Design (SBCCI'10), São Paulo, 2010. pp. 91-96.

  14. SOARES, R. I., CALAZANS, N. L. V., LOMNÉ, V., DEHBAOUI, A., MAURINE, P., TORRES, l. A GALS Pipeline DES Architecture to Increase Robustness against DPA and DEMA Attacks. In: Symposium on Integrated Circuits and Systems Design (SBCCI'10), São Paulo, 2010. pp. 115-120.

  15. RODOLFO, Taciano Ares; CALAZANS, N. L. V.; MORAES, F. G. Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. In: 2009 International Conference on Reconfigurable Computing and FPGAs (Reconfig´09), 2009. pp. 24-29.

  16. GUINDANI, G. M. ; CALAZANS, N. L. V. ; MORAES, F. G. A 10 Gbps OTN Framer Implementation Targeting FPGA Devices. In: 2009 International Conference on Reconfigurable Computing and FPGAs (Reconfig´09), 2009. pp. 30-35.

  17. CARVALHO, Ewerson Luiz de Souza; MARCON, César Augusto Missio; CALAZANS, N. L. V.; MORAES, F. G Evaluation of Static and Dynamic Task Mapping Algorithms in NoC-Based MPSoCs. In: International Symposium on System-on-Chip, 2009 (SOC'09), Tampere, 2009, pp. 87-90.

    18.

  18. CARVALHO, Ewerson Luiz de Souza ; CALAZANS, N. L. V. ; MORAES, F. G. Investigating Runtime Task Mapping for NoC-based Multiprocessor SoCs. In: 17th IFIP/IEEE International Conference on Very Large Scale Integration, 2009, Florianópolis. VLSI-SoC, 2009. Paper 47, 6p.

  19. CARARA, Everton Alceu ; CALAZANS, N. L. V. ; MORAES, F. G. Managing QoS Flows at Task Level in NoC-Based MPSoCs. In: 17th IFIP/IEEE International Conference on Very Large Scale Integration, 2009, Florianópolis. VLSI-SoC, 2009. Paper 49, 6p.

  20. CARARA, Everton Alceu, Oliveira, R. P., CALAZANS, N. L. V., MORAES, F. G. HeMPS - A Framework for Noc-Based MPSoC Generation. In: IEEE International Symposium on Circuits and Systems - ISCAS´09, Taipei, 2009. pp. 1345-1348.

  21. LOMNE, Victor, ORDAS, Thomas, MAURINE, Philippe, TORRES, Lionel, ROBERT, Michel, SOARES, Rafael Iankowski, CALAZANS, Ney Laert Vilar. Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA. In: DESIGN, AUTOMATION AND TEST IN EUROPE - DATE´09, Nice, 2009. pp. 634-639.

  22. LOMNE, Victor, ORDAS, Thomas, MAURINE, Philippe, TORRES, Lionel, ROBERT, Michel, SOARES, Rafael Iankowski, CALAZANS, Ney Laert Vilar. Triple Rail Logic Robustness against DPA. In: 2008 International Conference on Reconfigurable Computing and FPGAs. ReConFig 2008, Cancun, 2008.

  23. CARARA, Everton Alceu, PIGATTO, Daniel Vieira, CALAZANS, Ney Laert Vilar, MORAES, Fernando Gehm. MOTIM – an Industrial Application Using NOCs. In: 21st Symposium on Integrated Circuits and Systems - SBCCI 2008, Gramado, 2008. pp 182-187.

  24. SOARES, Rafael Iankowski, CALAZANS, Ney Laert Vilar, LOMNE, Victor, TORRES, Lionel, MAURINE, Philippe., ROBERT, Michel. Evaluating the Robustness of Secure Triple Track Logic through Prototyping. In: 21st Symposium on Integrated Circuits and Systems - SBCCI 2008, Gramado, 2008. pp 193-198.

  25. MORENO, Edson Ifarraguirre, POPOVICI, Katalin, CALAZANS, Ney Laert Vilar, JERRAYA, Ahmed Amine. Integrating Abstract NoC Models within MPSoC Design. In: 18th Annual IEEE/IFIP International Symposium on Rapid Systems Prototyping - RSP 2008, Monterrey, June, 2008. pp. 65-71.

  26. PONTES, Julian José Hilgemberg, MOREIRA, Matheus Trevisan; SOARES, Rafael Iankowski; CALAZANS, Ney Laert Vilar. Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. In: IEEE Computer Society Annual Symposium on VLSI Design - ISVLSI 2008, Montpellier. April, 2008. pp. 347-352.

  27. GUINDANI, Guilherme Montez; REINBRECHT, Cezar; RAUPP, Thiago; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. NoC Power Estimation at the RTL Abstraction Level. In: IEEE Computer Society Annual Symposium on VLSI Design - ISVLSI 2008, Montpellier. April, 2008. pp. 475-478.

  28. PONTES, Julian José Hilgemberg, SOARES, Rafael Iankowski, CARVALHO, Ewerson Luiz de Souza, MORAES, Fernando Gehm, CALAZANS, N. L. V. SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. In: XXV IEEE International Conference on Computer Design - ICCD 2007, Lake Tahoe, 2007. pp. 541-546.

  29. MELLO, Aline Vieira de, CALAZANS, N. L. V., MORAES, Fernando Gehm. Rate-based Scheduling Policy for QoS Flows in Networks on Chip. In: 15th Annual IFIP International Conference on Very Large Scale Integration - IFIP VLSI-SOC 2007, Atlanta. 2007. pp. 140-145.

  30. CARARA, Everton Alceu, CALAZANS, N. L. V., MORAES, Fernando Gehm. Router Architecture for High-Performance NoCs. In: 20th Symposium on Integrated Circuits and Systems - SBCCI 2007, Rio de Janeiro. New York: ACM Press, 2007. pp. 111-116.

  31. TEDESCO, Leonel Pablo, MORAES, Fernando Gehm, CALAZANS, N. L. V. Buffer Sizing for QoS Flows in Wormhole Packet Switching NoCs. In: 20th Symposium on Integrated Circuits and Systems - SBCCI 2007, Rio de Janeiro. New York: ACM Press, 2007. pp. 99-104.

  32. MÖLLER, Leandro Heleno; GREHS, Ismael; CARVALHO, Ewerson Luiz de Souza; SOARES, Rafael Iankowski; CALAZANS, N. L. V.; MORAES, Fernando Gehm. A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. In: Reconfigurable Communication-centric SoCs - ReCoSoC´07, Montpellier, 2007. pp. 23-30.

  33. MARCON, César Augusto Missio, MORENO, Edson Ifarraguirre, CALAZANS, N. L. V., MORAES, Fernando Gehm. Evaluation of Algorithms for Low Energy Mapping onto NoCs. In: 20th Symposium on Circuits and Systems and Systems - ISCAS 2007, New Orleans. 2007. pp. 389-392.

  34. CARUSO, Luís Carlos Mieres, GUINDANI, G. M., SCHMITT, Hugo Artur Weber, CALAZANS, N. L. V., MORAES, Fernando Gehm. SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems. In: 18th IEEE/IFIP International Workshop on Rapid System Prototyping - RSP2007, Porto Alegre. Los Alamitos, California: IEEE Computer Society Conference Publishing Services, 2007. pp. 27-33.

  35. CARVALHO, Ewerson Luiz de Souza, CALAZANS, N. L. V., MORAES, Fernando Gehm. Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs. In: 18th IEEE/IFIP International Workshop on Rapid System Prototyping - RSP 2007, Porto Alegre. Los Alamitos, California: IEEE Computer Society Conference Publishing Services, 2007. pp. 34-40.

  36. BASTOS, Érico Nunes Ferreira, CARARA, Everton Alceu, PIGATTO, D. V., CALAZANS, N. L. V., MORAES, Fernando Gehm. MOTIM – A Scalable Architecture for Ethernet Switches. In: IEEE Computer Society Annual Symposium on VLSI - ISVLSI 2007, Porto Alegre. Los Alamitos, California: IEEE Computer Society Conference Publishing Services, 2007. pp. 451-452.

  37. CARVALHO, Ewerson Luiz de Souza, CALAZANS, N. L. V., MORAES, Fernando Gehm. Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. In: IEEE Computer Society Annual Symposium on VLSI - ISVLSI 2007, Porto Alegre. Los Alamitos, California: IEEE Computer Society Conference Publishing Services, 2007. pp. 459-460.

  38. MELLO, Aline Vieira de; TEDESCO, Leonel Pablo; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Evaluation of Current Mechanisms Employed to Provide QoS in Networks on Chip. In: INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP - SoC2006, Tampere. 2006. pp. 115-118.

  39. TEDESCO, Leonel Pablo; MELLO, Aline Vieira de; GIACOMET, Leonardo Luigi; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Application Driven Traffic Modeling for NoCs. In: 19TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2006, Ouro Preto. New York: ACM Press, 2006. pp. 62-67.

  40. MÖLLER, Leandro Heleno; SOARES, Rafael Iankowski; CARVALHO, Ewerson Luiz de Souza; GREHS, Ismael; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Infrastructure for Dynamic Reconfigurable Systems: Choices and Trade-offs. In: 19TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2006, Ouro Preto. 2006. pp. 44-49.

  41. MÖLLER, Leandro Heleno; GREHS, Ismael; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Reconfigurable Systems Enabled by a Network-on-Chip. In: 16TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS - FPL 2006. Madri, 2006. pp. 857-860.

  42. MARCON, César Augusto Missio; PALMA, José Carlos Sant´anna; CALAZANS, Ney Laert Vilar; SUSIN, Altamiro Amadeu; REIS, Ricardo Augusto da Luz; MORAES, Fernando Gehm. Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. In: IFIP INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION, 2005, Perth. IFIP VLSI-SOC 2005. 2005.

  43. MELLO, Aline Vieira de; TEDESCO, Leonel Pablo; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Virtual Channels in Networks on Chip: Implementation and Evaluation on Hermes NoC. In: 18TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2005. New York: ACM Press, 2005. pp. 178-183.

  44. TEDESCO, Leonel Pablo; MELLO, Aline Vieira de; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Traffic Generation and Performance Evaluation for Mesh-based NoCs. In: 18TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2005.  New York: ACM Press, 2005. pp. 184-189.

  45. PALMA, José Carlos Sant'anna; MARCON, César Augusto Missio; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; REIS, Ricardo Augusto da Luz; SUSIN, Altamiro Amadeu. Mapping Embedded Systems onto NoCs - The Traffic Effect on Dynamic Energy Estimation. In: 18TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2005.  New York: ACM Press, 2005. pp. 196-201.

  46. MARCON, César Augusto Missio; KREUTZ, Márcio; SUSIN, Altamiro Amadeu; CALAZANS, Ney Laert Vilar. Models for Embedded Application Mapping onto NoCs: Timing Analysis. In: 16TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, 2005 - RSP 2005, Montreal. 2005. pp. 17-23.

  47. MARCON, César Augusto Missio; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; SUSIN, Altamiro Amadeu; REIS, Igor Maicá; HESSEL, Fabiano Passuelo. Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. In: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION - DATE´05, Munich. 2005. pp. 502-507, Volume 1.

  48. KREUTZ, Márcio; MARCON, César Augusto Missio; CALAZANS, Ney Laert Vilar; SUSIN, Altamiro Amadeu. Energy and Latency Evaluation of NoC Topologies. In: 2005 IEEE SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2005, Kobe. ISCAS 2005. 2005. p. 5866-5869.

  49. MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. MultiNoC: A Multiprocessing System Enabled by a Network on Chip. In: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION - DATE´05, 2005, Münich. DATE 2005 Designers’ Forum Proceedings, Munich. 2005. pp. 234-239.

  50. OST, Luciano Copello; MELLO, Aline Vieira de; PALMA, José Carlos Sant´anna; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. MAIA - A Framework for Networks on Chip Generation and Verification. In: ASIA SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2005, Beijing. ASP-DAC 2005. 2005. v. 1, p. 49-52.

  51. CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; MARCON, César Augusto Missio; PALMA, José Carlos Sant´anna. Design, Validation and Prototyping of the EMS SDH STM-1 Mapper Soft-core. In: 6TH IEEE LATIN-AMERICAN TEST WORKSHOP, 2005, Salvador. LATW 2005. 2005. p. 313-318.

  52. MÖLLER, Leandro Heleno; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Reconfigurable Processors: State of the Art. In: XI WORKSHOP IBERCHIP, 2005, Salvador. 2005. p. 110-113. (In Portuguese)

  53. CARUSO, Luís Carlos Mieres; GUINDANI, Guilherme Montex; SCHMITT, Hugo Artur Weber; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Sea of Processors Architecture for Network Intrusion Detection. In: XI WORKSHOP IBERCHIP, 2005, Salvador. 2005. v. 1, p. 247-250. (In Portuguese)

  54. CARARA, Everton Alceu; MELLO, Aline Vieira de; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Virtual Channels in Intra-chip Networks - Implementation in the Hermes Network. In: XI WORKSHOP IBERCHIP, 2005, Salvador. 2005. v. 1, p. 320-321. (In Portuguese)

  55. CARVALHO, Ewerson Luiz de Souza; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; MESQUITA, Daniel. Reconfiguration Control for Dynamically Reconfigurable Systems. In: XIX CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS, 2004, Bordeaux. DCIS´2004. 2004. p. 405-410.

  56. CARVALHO, Ewerson Luiz de Souza; CALAZANS, Ney Laert Vilar; BRIÃO, Eduardo Wenzel; MORAES, Fernando Gehm. PADReH - A Framework for the Design and Implementation of Dynamically and Partially Reconfigurable Systems. In: 17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2004, 2004, Ipojuca. 17th Symposium on Integrated Circuits and Systems Design - SBCCI 2004. New York: ACM Press, 2004. pp. 10-15.

  57. MÖLLER, Leandro Heleno; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; BRIÃO, Eduardo Wenzel; CARVALHO, Ewerson Luiz de Souza; CAMOZZATO, Daniel. FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. In: FPL - THE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2004, Antwerp, Belgium. FPL'04. Berlin: Springer-Verlag, 2004. pp. 1042-1046.

  58. MARCON, César Augusto Missio; AMORY, Alexandre Morais; LUBASZEWSKI, Marcelo Soares; SUSIN, Altamiro Amadeu; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; HESSEL, Fabiano Passuelo. Applying Memory Test to Embedded Systems. In: 5TH IEEE LATIN-AMERICAN TEST WORKSHOP, 2004, Cartagena. LATW 2004. 2004.

  59. CARVALHO, Ewerson Luiz de Souza; MÖLLER, Frederico Bartz; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Configuration Control in Dynamically and Partially Reconfigurable Systems. In: X WORKSHOP IBERCHIP, 2004, Cartagena. X Workshop Iberchip. 2004. (In Portuguese)

  60. MORENO, Edson Ifarraguirre; RODOLFO, Taciano Ares; CALAZANS, Ney Laert Vilar. SoC Modeling and Description at Different Abstraction Levels. In: X WORKSHOP IBERCHIP, 2004, Cartagena. X Workshop Iberchip. 2004. (In Portuguese)

  61. MORAES, Fernando Gehm; OST, Luciano Copello; MELLO, Aline Vieira de; PALMA, José Carlos Sant'anna; CALAZANS, Ney Laert Vilar. NOCGEN - A Tool for the Generation of Intra-chip Networks based on the HERMES Infra-structure. In: X WORKSHOP IBERCHIP, 2004, Cartagena. X Workshop Iberchip. 2004. (In Portuguese)

  62. BRIÃO, Eduardo Wenzel; CAMOZZATO, Daniel; RIES, Luís Henrique Leal; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Partial and Dynamic Reconfiguration of Intellectual Property Cores with Standardized Communication Interfaces. In: X WORKSHOP IBERCHIP, 2004, Cartagena. X Workshop Iberchip. 2004. (In Portuguese)

  63. MORAES, Fernando Gehm; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; OST, Luciano Copello; CALAZANS, Ney Laert Vilar. A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. In: IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2003. Darmstadt, Germany. pp. 318-323, 2003.

  64. CALAZANS, Ney Laert Vilar; MORENO, Edson; HESSEL, Fabiano; ROSA, Vitor, MORAES, Fernando Gehm; CARARA, Everton. From VHDL Register Transfer Level to SystemC Transaction Level Modeling: a comparative case study. In: 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI´2003. Los Alamitos: IEEE Computer Society Press.  São Paulo, Brazil. pp. 355-360, 2003.

  65. MESQUITA, Daniel; MORAES, Fernando Gehm; PALMA, José Carlos Sant'anna; MÖLLER, Leandro Heleno; CALAZANS, Ney Laert Vilar. Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. In: Design, Automation and Test in Europe Conference and Exhibition, DATE´03. München, Germany. pp. 1122-1123. 2003.

  66. MESQUITA, Daniel; MORAES, Fernando Gehm; PALMA, José Carlos Sant'anna; MÖLLER, Leandro Heleno; CALAZANS, Ney Laert Vilar. Remote and Partial Reconfiguration of FPGAs: tools and trends. In: 10TH RECONFIGURABLE ARCHITECTURES WORKSHOP, RAW´03. Nice, France. 2003.

  67. MARCON, César Augusto Missio; HESSEL, Fabiano Passuelo; AMORY, Alexandre Morais; RIES, Luís Henrique Leal; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Prototyping of Embedded Digital Systems from SDL Language: a case study. In: SEVENTH ANNUAL IEEE INTERNATIONAL WORKSHOP ON HIGH LEVEL DESIGN VALIDATION AND TEST, HLDVT´02. Cannes, France. pp. 133-138. 2002.

  68. BEZERRA, Eduardo Augusto; POUCHET, Marianne; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; GOUGH, Michael. An Adaptable Educational Platform for Engineering and IT Laboratory Based Courses. In: 2002 FRONTIERS IN EDUCATION CONFERENCE, FIE´02. Boston, MA. 2002.

  69. CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; MARCON, César Augusto Missio. Teaching Computer Organization and Architecture with Hands-on Experience. In: 2002 FRONTIERS IN EDUCATION CONFERENCE, FIE´02. Boston, MA. 2002.

  70. PALMA, José Carlos Sant'anna; MELLO, Aline Vieira de; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Core Communication Interface for FPGAs. In: 15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI´2002. Los Alamitos: IEEE Computer Society Press.  Porto Alegre, Brazil. 2002.

  71. AMORY, Alexandre Morais; MORAES, Fernando Gehm; OLIVEIRA, Leandro Augusto de; CALAZANS, Ney Laert Vilar; HESSEL, Fabiano Passuelo. A Heterogeneous and Distributed Co-Simulation Environment. In: 15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI´2002. Los Alamitos: IEEE Computer Society Press.  Porto Alegre, Brazil. 2002.

  72. MARCON, César Augusto Missio; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Requirements, Primitives and Models for Systems Specification. In: 15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI´2002. Los Alamitos: IEEE Computer Society Press.  Porto Alegre, Brazil. 2002.

  73. MORAES, Fernando Gehm; ZORZO, Avelino Francisco; CALAZANS, Ney Laert Vilar. Deriving Different Computer Science Curricula from a Common Core of Disciplines. In: INFORMATICS CURRICULA, TEACHING METHODS AND BEST PRACTICE, ICTEM'2002. Florianópolis, Brazil. pp. 43-49. 2002.

  74. AMORY, Alexandre Morais; MORAES, Fernando Gehm; OLIVEIRA, Leandro Augusto de; HESSEL, Fabiano Passuelo; CALAZANS, Ney Laert Vilar. Development of a Distributed and Heterogeneous Cossimulation  Environment. In: VIII WORKSHOP IBERCHIP. Guadalajara, Mexico. 2002. (in Portuguese)

  75. PALMA, José Carlos Sant'anna; MELLO, Aline Vieira de; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Core Communication Interface in FPGAs. In: VIII WORKSHOP IBERCHIP. Guadalajara, Mexico. 2002. (in Portuguese)

  76. MARCON, César Augusto Missio; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; RIES, Luís Henrique Leal; HESSEL, Fabiano Passuelo. Modeling and Description of Computing Systems: a case study comparing VHDL and SDL languages. In: VIII WORKSHOP IBERCHIP. Guadalajara, Mexico. 2002. (in Portuguese)

  77. MORAES, Fernando Gehm; AMORY, Alexandre Morais; CALAZANS, Ney Laert Vilar; BEZERRA, Eduardo Augusto; PETRINI JÚNIOR, Juracy. Using the CAN Protocol and Reconfigurable Computing Technology For Web-Based Smart House Automation. In: 14TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI´2001. Los Alamitos: IEEE Computer Society Press. Pirenópolis, Brazil. 2001.

  78. CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; MARCON, César Augusto Missio; BLAUTH, Vitor Hugo; VALIATI, Ronaldo; MANFROI, Édison. Effective Industry-Academia Cooperation in Telecom: a method, a case study and some initial results. In: XIX SIMPÓSIO BRASILEIRO DE TELECOMUNICAÇÕES, SBrT´2001. Fortaleza, Brazil. 2001.

  79. CAPPELATTI, Ewerton Artur; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; OLIVEIRA, Leandro Augusto de. High Performance Bus for Hardware/Software Interaction. In: VII WORKSHOP IBERCHIP IWS'2001, IWS'2001. Montevidéu, Uruguay. 2001. (in Portuguese)

  80. TOROK, Delfim Luiz; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; ANDREOLI, Andrey Vedana. Design, Implementation and Validation of an Ethernet IP Soft Core on reconfigurable Devices. In: VII WORKSHOP IBERCHIP, WS'2001, IWS'2001. Montevidéu, Uruguay. 2001 (in Portuguese)

  81. MESQUITA, Daniel; MORAES, Fernando Gehm; PALMA, José Carlos Sant'anna; MÖLLER, Leandro; CALAZANS, Ney Laert Vilar. Partial and Remote Core Reconfiguration in FPGAs. In: VII WORKSHOP IBERCHIP, IWS'2001. Montevidéu, Uruguay. 2001. (in Portuguese)

  82. MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MARCON, César Augusto Missio; MELLO, Aline Vieira de. A Compiling and Simulation Environment for Parameterizable Embedded Processors. In: VII WORKSHOP IBERCHIP, IWS'2001. Montevidéu, Uruguay. 2001. (in Portuguese)

  83. MORAES, Fernando Gehm; MELLO, Aline Vieira de; CALAZANS, Ney Laert Vilar. Embedded Processor Development Environment for Codesign Applications. In: SEMINÁRIO DE COMPUTAÇÃO RECONFIGURÁVEL, SCR'2001.Belo Horizonte, Brazil. 2001. (in Portuguese)

  84. PALMA, José Carlos Sant'anna; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Methods for Development and Distribution of IP Cores. In: SEMINÁRIO DE COMPUTAÇÃO RECONFIGURÁVEL, SCR'2001.Belo Horizonte, Brazil. 2001. (in Portuguese)

  85. BEZERRA, Eduardo Augusto; POUCHET, Marianne; STIPIDIS, Elias; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; EINSFELDT, Augusto. RECKON - A reconfigurable prototyping kit for engineering and IT laboratory based courses. In: SEMINÁRIO DE COMPUTAÇÃO RECONFIGURÁVEL, SCR'2001.Belo Horizonte, Brazil. 2001.

  86. MESQUITA, Daniel; MORAES, Fernando Gehm; MÖLLER, Leandro; CALAZANS, Ney Laert Vilar. Remote and Partial Reconfiguration of Virtex Family FPGA Devices. In: SEMINÁRIO DE COMPUTAÇÃO RECONFIGURÁVEL, SCR'2001.Belo Horizonte, Brazil. 2001. (in Portuguese)

  87. CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; QUINTANS, Katherine Beserra; NEUWALD, Felipe Barp. Accelerating Sorting through the Use of Reconfigurable Hardware. In: Reconfigurable Computing - Experiences and Perspectives. Marília, Brazil. pp. 30-35. 2000.

  88. MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; FERREIRA, Ewerton Hofler; LIEDKE, Daniel Carvalho. Efficient Implementation of a Load/store Architecture in VHDL. In: Reconfigurable Computing - Experiences and Perspectives. Marília, Brazil. pp. 2-13. 2000. (in Portuguese)

  89. CALAZANS, Ney Laert Vilar, MORAES, Fernando Gehm. VLSI Hardware Design by Computer Science Students: How early can they start? How far can they go?. In: 1999 FRONTIERS IN EDUCATION CONFERENCE, San Juan. IEEE Computer Society Press. pp.13612-13617. 1999.

  90. MORAES, Fernando Gehm, CALAZANS, Ney Laert Vilar, SILVA, Felipe Rocha, BARRIOS, Maurício. Cleo-LIRMM: An Experiment of Dedicated Processors Implementation  on Embedded Systems Prototyping Platforms. In: V WORKSHOP IBERCHIP, Lima, Peru. pp.81-90.1999. (in Portuguese)

  91. MARQUES, Paulo César, MORAES, Fernando Gehm, CALAZANS, Ney Laert Vilar. PMAZE: Modeling and Routing for FPGAs. In: V WORKSHOP IBERCHIP, Lima, Peru. pp.70-80.1999. (in Portuguese)

  92. CALAZANS, Ney Laert Vilar, MADEIRA, André Duque. ASSTUCE - An Exploratory Environment for Finite State Machines. In: XXIII CONFERENCIA LATINOAMERICANA DE INFORMÁTICA, CLEI, Valparaiso, Chile. v.1. pp.117-126.1997.

  93. VARGAS, Fabian, MORAES, Fernando Gehm, CALAZANS, Ney Laert Vilar, BEZERRA, Eduardo Augusto. HardSoft: Reconfigurable Platform for Characterization under Radiation of Electronic Components Employed in Satellites. In: VII SIMPÓSIO DE COMPUTADORES TOLERANTES A FALHAS, SCTF. Campina Grande, Brazil. pp.139-152.1997. (in Portuguese)

  94. CARNEIRO, Mára Lúcia Fernandes, CALAZANS, Ney Laert Vilar. Automated Design of Distillation Columns based on Probabilistic Optimization. In: XI CONGRESSO BRASILEIRO DE ENGENHARIA QUÍMICA, COBEQ. Rio de Janeiro, Brazil. 1996. (in Portuguese)

  95. VARGAS, Fabian, VELAZCO, Raoul, AMARAL, José Nelson, CALAZANS, Ney Laert Vilar, RODRIGUES, Alderico. Radiation effects on electronics: the need for ground tests. In: IX SIMPÓSIO BRASILEIRO DE CONCEPÇÃO DE CIRCUITOS INTEGRADOS - SBCCI´96. Recife. Brazil.  pp.105-116. 1996.

  96. CALAZANS, Ney Laert Vilar. Considering State Minimization during State Assignment. In: I IBERO AMERICAN MICROELECTRONICS CONFERENCE - X CONGRESS OF THE BRAZILIAN MICROELECTRONICS SOCIETY, Canela, RS. pp.49-58. 1995.

  97. CALAZANS, Ney Laert Vilar. Boolean Constrained Encoding: a new formulation and a case study. In: INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - ICCAD´94, San Jose, CA. pp.702-706. 1994.

  98. CALAZANS, Ney Laert Vilar, ZHANG, Qinhai, JACOBI, Ricardo Pezzuol, YERNAUX, Bruno, TRULLEMANS, Anne Marie. Advanced Ordering and Manipulation Techniques for Binary Decision Diagrams. In: EUROPEAN CONFERENCE ON DESIGN AUTOMATION, EDAC'92. Brussels, Belgium. pp.452-457. 1992.

  99. CALAZANS, Ney Laert Vilar. State Minimization and State Assignment of Finite State Machines. their relationship and their impact on the implementation. In: IFIP INTERNATIONAL WORKSHOP ON APPLICATION-ORIENTED SYNTHESIS. Dresden, Germany. 1992.

  100. CALAZANS, Ney Laert Vilar, JACOBI, Ricardo Pezzuol, ZHANG, Qinhai, TRULLEMANS, Charles. Improving BDDs manipulation through incremental reduction and enhanced heuristics. In: CUSTOM INTEGRATED CIRCUITS CONFERENCE, CICC´91. San Diego, CA. pp.1131-1135. 1991. (Presentation Slides)

  101. JACOBI, Ricardo Pezzuol, CALAZANS, Ney Laert Vilar, TRULLEMANS, Charles. Incremental Reduction of Binary Decision Diagrams. In: INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS'91. Singapore, Singapore. pp.3174-3177. 1991.

  102. CALAZANS, Ney Laert Vilar, WEBER, Taisy da Silva. Logic Minimization for Combinational Circuits. In: IV SIMPÓSIO BRASILEIRO DE CONCEPÇÃO DE CIRCUITOS INTEGRADOS, SBCCI. Rio de Janeiro, Brazil. pp.52-61. 1989. (in Portuguese)

  103. CALAZANS, Ney Laert Vilar, REY, Leandro Fortes, WAGNER, Flávio Rech. A Logic Simulator for an Integrated Environment of Digital Hardware Design. In: III CONGRESSO DA SOCIEDADE BRASILEIRA DE MICROELETRÔNICA, SBMICRO. São Paulo, Brazil. pp.385-395. 1988.

  104. CALAZANS, Ney Laert Vilar. Specification of EDGAR - A Mask Editor for Gate Array Integrated Circuits. In: XIV
    SEMINÁRIO INTEGRADO DE SOFTWARE E HARDWARE    , SEMISH. Salvador, Brazil. pp.117-130. 1987.  (in Portuguese)

  105. CALAZANS, Ney Laert Vilar, BARONE, Dante Augusto Couto. Proposal of a New Base Cell for Pre-diffused circuits in the CIPREDI Methodology. In: II CONGRESSO DA SOCIEDADE BRASILEIRA DE MICROELETRÔNICA, SBMICRO. São Paulo, Brazil. pp.212-222. 1987. (in Portuguese)

  106. CALAZANS, Ney Laert Vilar, BIER, Paulo Juvenal. Microphotographical Analysis of the Internal Architecture of the ADM Controller AMD9517. In: XI SEMINÁRIO INTEGRADO DE SOFTWARE E HARDWARE, SEMISH. Viçosa, Brazil. pp.149-160. 1984. (in Portuguese)

    107.

Books and Book Chapters

  1. MÖLLER, Leandro Heleno; GREHS, Ismael; CARVALHO, Ewerson Luiz de Souza; SOARES, Rafael Iankowski; CALAZANS, Ney; MORAES, F. G. A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. Dynamic Reconfigurable Network-on-chip Design: Innovation for Computational Processing and Communication. Hershey, PA: IGI Global, 2009. pp. 1-27.

  2. MELLO, Aline Vieira de, CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques. Book chapter In: VLSI-SoC: Advanced Topics on Systems on a Chip. Ed. Dordrecht: Springer, April, 2009, v.291. pp. 109-130. Edited by Ricardo REIS, Vincent MOONEY and Paul HASLER. (Contains extensions of the best papers presented at the  Fifteenth International Conference on Very Large Scale Integration of System on Chip - VLSI-SoC 2007 Conference, which took place in 15-17 October 2007, in Atlanta, EUA). (ask for draft version by e-mail)

  3. MARCON, César Augusto Missio; PALMA, José Carlos Sant´anna; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; SUSIN, Altamiro Amadeu; REIS, Ricardo Augusto da Luz. Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. Chapter 12, pp 179-194. In: VLSI-SoC: From Systems to Silicon. Edited by Ricardo Augusto da Luz REIS, Adam OSSEIRAN and Hans-Joerg PFLEIDERER. Springer Book, ISBN: 978-0-387-73660-0. 2007. 344 pages. (ask for draft version by e-mail)

  4. MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MÖLLER, Leandro Heleno; BRIÃO, Eduardo Wenzel, CARVALHO, Ewerson Luiz de Souza. Dynamic and Partial Reconfiguration in FPGA SoCs: Requirements and Tools. Chapter 13, pp 157-168.  In: New Algorithms, Architectures and Applications for Reconfigurable Computing. Edited by Patrick LYSAGHT & Wolfgang ROSENSTIEL. Springer Book, ISBN: 1-4020-3127-0, 2005. 313 pages. (ask for draft version by e-mail)

  5. CALAZANS, Ney Laert Vilar. Automated Logic Design of Sequential Digital Circuits. Rio de Janeiro: Imprinta Gráfica e Editora Ltda - UFRJ. 342 pages. 1998. (Book published in the context of the 11th. Computing School, realized from 20-24 July 1998) (Courses Slides also available) (In Portuguese)

    6.

Advised or Presented Thesis

  1. SOARES, Rafael Iankowski. GALS Pipeline Architectures for Cryptography Robust to DPA and DEMA Attacks. 2010. PhD Thesis, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. November 2010. Scholarship Sponsor: CNPq (PNM). (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese).

  2. MORENO, Edson Ifarraguirre. Mapping and Communication Routes Adaptation in Networks on Chip. PhD Thesis, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. January 2010. Scholarship Sponsor: CNPq (PNM). (Presented and approved. Research Advisor: Ney Laert Vilar Calazans). (In Portuguese).

  3. MARCON, César Augusto Missio. Models for Applications  Mapping in Intrachip Communication Infra-structures. PhD Thesis, PPGC - II - UFRGS, Porto Alegre, Brazil. December 2005. 192 pages. Scholarship Sponsor: CAPES. (Presented and approved. Research Advisor: Altamiro Amadeu Susin. Research Co-Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  4. CALAZANS, Ney Laert Vilar. State Minimization and State Assignment of Finite State Machines: their relationship and their impact on the implementation . PhD Thesis, Université Catholique de Louvain - UCL, Louvain-la-Neuve, Belgium. October 1993.

    5.

Advised or Presented Dissertations

  1. MOREIRA, Matheus Trevisan. Contributions to the Design and Prototyping of GALS and Asynchronous Systems. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. April 2012. Scholarship Sponsor: Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES). (Presented and approved. Research Advisor: Ney Laert Vilar Calazans). Final version of text in preparation.

  2. MOHR, Adilson Arthur. PMEMD-HW: Molecular Dynamics Simulation Using Reconfigurable Hardware. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2010. Scholarship Sponsor: CNPq (PNM). (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese).

  3. RODOLFO, Taciano Ares. An Exploration of the Design Space for Processors with Floating Point Point Hardware in FPGAs. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2010. Scholarship Sponsor: CNPq (PNM). (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese). Final volume in preparation.

  4. BEZERRA, Jeronimo Cunha. Verification and Prototyping of Intrachip Networks: The Hermes-TB case study. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. August 2009. 77  pages.  Partial Scholarship Sponsor: CAPES. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese).

  5. SARTIN, Maicon Aparecido. A Communication API for Hardware Acceleration of Molecular Simulators. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. July 2009. 106 pages.  Partial Scholarship Sponsors: CAPES-FAPEMAT. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese).

  6. PETRY, Carlos Alberto. Abstract Modeling of an MPSoC Hardware. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. February 2009. 113 pages.  Partial Scholarship Sponsor: FINEP. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese).

  7. PONTES, Julian José Hilgemberg. Design and Prototyping of Non-synchronous Interfaces and Intrachip Networks in FPGAs. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. February 2008. 120 pages.  Scholarship Sponsor: CAPES. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese).

  8. DISCONZI, Rosana Perazzolo. Modeling and Validation of Intrachip Networks through Behavioral Synthesis. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. October 2007. 145 pages.  (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  9. SCHERER JUNIOR, Carlos Adail. Torus Topology Wormhole Intra-chip Networks-on-Chip: Design, Generation and Evaluation. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2007. 101 pages.  Scholarship Sponsor: CNPq (PNM). (Presented and approved. Final volume in preparation. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  10. BASTOS, Érico Nunes Ferreira. Mercury: An intra-chip Network with 2D Torus Topology and Adaptive Routing. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. January 2006. 148 pages. Scholarship Sponsor: CAPES. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  11. SOARES, Rafael Iankowski. Reconfigurable Hardware Configuration Control in Software: Infrastructure and Implementation. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. January 2006. 145 pages. Scholarship Sponsor: CAPES. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese).

  12. MORENO, Edson Ifarraguirre. Modeling, Description and Validation of Intra-Chip Networks at the Transaction Level. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2004. 137 pages. Scholarship Sponsor: CAPES. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  13. CARVALHO, Ewerson Luiz de Souza. RSCM - A Configuration Controller for Reconfigurable Hardware Systems. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2004. 155 pages. Scholarship Sponsor: CNPq. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  14. BRIÃO, Eduardo Wenzel. Dinamyc and Partial Reconfiguration for Intellectual Property Cores. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. January 2004. 149 pages. Scholarship Sponsor: CNPq. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans). (In Portuguese)

  15. SOUZA, Sheila Moreira. ATM Adaptation Layers for the Transfer of Data and Voice. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. January 2003. 151 pages. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  16. CASTANHEIRA, Leonardo Dutra. Flexible Traffic Generation with Application to ATM Networks. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. February 2003. 138 pages. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  17. TOROK, Delfim Luiz. Design for Prototyping of the Medium Access Protocol in Ethernet Networks. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. August 2001. 136 pages. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  18. CARNEIRO, Mára Lúcia Fernandes. Automated Synthesis of Distillation Columns: an alternative approach to the design process. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. September 1996. 107 pages. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  19. CALAZANS, Ney Laert Vilar. CIPREDI: Initial Contribution to a Design Method for Pre-Diffused Integrated Circuits. MSc Dissertation, Universidade Federal do Rio Grande do Sul - UFRGS, CPGCC, Porto Alegre, RS, Brazil. October, 1988. (in Portuguese)

    20.

Advised or Presented End of Term Works

  1. FERREIRA, Bruno Fin and HEINEN, Ismael Luís. HNPlus – A Network on Chip Prototyping Platform with a Generic Traffic Generation Scheme. 2011. Computer Engineering Course - PUCRS. (Presented and approved. Advisor: Ney Laert Vilar Calazans)

  2. BONDAN, Lucas, GOBBI, Rodrigo Celso and FOCHI, Vinícius Morais. The Link Aggregation Protocol LACP: A simulator and the Packet Marking Protocol. 2011. Computer Engineering Course - PUCRS. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  3. MOREIRA, Matheus Trevisan. Design and Implementation of a Standard Cell Library for Building Asynchronous ASICs. End of Term Work. Computer Engineering - PUCRS. December 2010. 139 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans)

  4. TOFFOLO, Valter. A Clock Generator with Dynamic Frequency Scaling for Globally Asynchronous Locally Synchronous Systems. End of Term Work. Computer Engineering - PUCRS. December 2010. 72 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  5. OLIVEIRA, Roberto Port de. Development of an IGMP Protocol for Ethernet Switches. End of Term Work. Computer Engineering - PUCRS. December 2010. 80 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  6. LANGE, Augusto, BOHRER, Vinicius P. & SILVA, Vinícius S. da. Adapting Systems to operate with On Chip Networks: Decoder M-JPEG/HERMES. End of Term Work. Computer Engineering - PUCRS.  July 2010. 83 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  7. SOCCOL, Celso Marasca & ZUCOLOTTO, Giovani. A GNU Chess Implementation in a Multiprocessing Platform with Communication Architecture based on an Intrachip Network. End of Term Work.  Computer Science Course - PUCRS. December 2006. 87 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  8. SARMENTO, Marcelo. Self-Reconfigurable Architectures in Digital Systems. End of Term Work. Computer Science - PUCRS. June 2001. 101 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  9. MADEIRA, André Duque. Graph Coloring: theory and applications to VLSI synthesis. End of Term Work. Computer Science - PUCRS. December 1998. 101 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  10. CARDOSO, Luciano Barbosa. COFECO: A Set of Tools for Integrated Hardware and Software Design. End of Term Work. Computer Science - PUCRS. 1997. 47 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  11. VENCATO, Fábio Clever. XAsstuce: A Graphic and Textual Interface for the Asstuce Exploratory Environment  of Finite State Machines. End of Term Work. Computer Science - PUCRS. 1996. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

  12. SAURESSIG, Guilherme. MEMCE: An Algorithm for the State Minimization for the Asstuce Environment. End of Term Work. Computer Science - PUCRS. 1996. 133 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

    13.

Advised or Presented Monographs

  1. To be updated.

    2.

Technical Reports and Other Publications

  1. BASTOS, Érico  Nunes Ferreira; SOCCOL, Celso; CALAZANS, Ney Laert Vilar. Design and Implementation of the MERCURY Communication Architecture: an intra-chip network with torus topology, centralized shared queues and virtual-cut-through switching mode. PPGCC-PUCRS Technical Report Series, TR050, 36 pages. August, 2005. (in Portuguese)

  2. CARVALHO, Ewerson Luiz de Souza; MÖLLER, Frederico Bartz; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Design Frameworks and Configuration Controllers for Dynamic And Partial Reconfiguration. PPGCC-PUCRS Technical Report Series, TR042, 17 pages. June, 2004.

  3. MELLO, Aline Vieira de; OST, Luciano Copello; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Evaluation of Routing Algorithms in Mesh Based NoCs. PPGCC-PUCRS Technical Report Series, TR040, 11 pages. May, 2004.

  4. CALAZANS, Ney Laert Vilar; IDE, Alessandro Noriaki; MORENO, Edson Ifarraguirre; RODOLFO, Taciano Ares; MORAES, Fernando Gehm. Tutorial and Directives for Design Capture, Validation and Prototyping of Hardware Modules Described in SystemC. PPGCC-PUCRS Technical Report Series, TR036, 48 pages. November, 2003. (in Portuguese)

  5. MÖLLER, Leandro Heleno; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Tools for Partial, Remote and Dynamic Reconfiguration of Virtex FPGAs. PPGCC-PUCRS Technical Report Series, TR035, 29 pages. November, 2003. (in Portuguese).

  6. MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; OST, Luciano Copello. HERMES: an Insfrastructure for Low Area Overhead Packet-switching Networks on Chip. PPGCC-PUCRS Technical Report Series, TR034, 26 pages. October, 2003.

  7. CALAZANS, Ney Laert Vilar; BRIÃO, Eduardo Wenzel. Tutorials on Partial and Dynamic Reconfiguration using the Modular Design Design Flow on the Insight V2MB100 Platform. PPGCC-PUCRS Technical Report Series, TR033, 93 pages. October, 2003. (in Portuguese)

  8. MORAES, Fernando Gehm; FERREIRA, Ewerton Hofler; CALAZANS, Ney Laert Vilar. Implementation of a Load/store  Architecture in a Prototyping Environment. PPGCC-PUCRS Technical Report Series, TR002, 48 pages. May, 2000. (in Portuguese)

  9. CALAZANS, Ney Laert Vilar. Methods and Tools for the Design of Digital Systems. In: III ESCOLA REGIONAL DE INFORMÁTICA - ERI, Caxias do Sul, Brazil. 1995. pp.34-53. Text of Invited Short Course. (in Portuguese)

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 This page was last updated on May, 11th, 2012.
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