--
-- Author: Ney Calazans
-- Last Modified: 01/04/2006
--
-- This module implements the interface hardware needed to drive the 
-- Digilent DIO4 board four digit seven segment display. This 
-- display is multiplexed (see the DIO4 Reference Manual for details)
-- requiring that just one digit be displayed at any moment.
-- 
-- The inputs of the module are:
--		clock - the 50MHz D2SB system board clock
--		reset - the active-high system reset signal
--    di vectors - 4 vectors, each with 6 bits, where:
--			di(0) is the decimal point (active-low)
--			di(4 downto 1) is the binary value of the digit
--			di(5) is the (active-high) enable signal of the digit
--     here, i varies from 4 to 1, 4 corresponds to the rightmost
--		 digit of the display and 1 corresponds to the leftmost digit
-- 
-- The outputs of the module are:
--		an (4 downto 1) - the four wire active-low anode vector.
-- 		In this circuit, exactly one of these 4 wires is at logic 0
--			at any moment. The wire in 0 lights up one of the 4 7-segment
--			displays. 4 is the rightmost display while 1 is the leftmost.
--		dec_ddp (7 downto 0) - is the decoded value of the digit to show
--			at the current instant. dec_ddp(7 downto 1)  corresponds
--			respectively to the segments a b c d e f g, and dec_ddp(0) is
--			the decimal point.
--
-- Functional description: The 50MHz clock is divided to obtain the
--		512Hz display refresh clock. Upon reset, all displays are turned
--		off. The 512Hz clock feeds a 2-bit counter. This counter
--		generates a signal used to select one of the four di vectors. This
--		vector is in turn used to enable (or not) showing the digit in
--		question (through di(5)) and furnishes the digit value for the
--		specific multiplexed 7-segment decoder. All outputs are registered
--		using the 512Hz clock.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity dio4_dspl_drv is
	port (
		clock: in STD_LOGIC;
		reset: in STD_LOGIC;
		d4: in STD_LOGIC_VECTOR (5 downto 0);
		d3: in STD_LOGIC_VECTOR (5 downto 0);
		d2: in STD_LOGIC_VECTOR (5 downto 0);
		d1: in STD_LOGIC_VECTOR (5 downto 0);
		an: out STD_LOGIC_VECTOR (4 downto 1);
		dec_ddp: out STD_LOGIC_VECTOR (7 downto 0)
	);
end dio4_dspl_drv;

--}} End of automatically maintained section

architecture dio4_dspl_drv of dio4_dspl_drv is
signal ck_512Hz: std_logic; -- internally generated 512Hz clock
signal dig_selection: std_logic_vector (1 downto 0); -- circulating counter to select digit to show
signal selected_dig: std_logic_vector (5 downto 0); -- chosen 6-bit digit encoding
signal decoded_dig: std_logic_vector (7 downto 0); -- decoded 7-segment value
signal an_en: std_logic_vector (4 downto 1); -- display selection information
signal tmp_vec3: std_logic_vector (2 downto 0); -- auxiliary vector

begin
	-- 512Hz clock generation
	process (reset, clock)
	variable count_50K: integer range 0 to 50000;
	begin
		if reset='1' then
			count_50K := 0;
			ck_512Hz <= '0';
		elsif (clock'event and clock='1') then
			count_50K := count_50K + 1;
			if (count_50K = 49999) then
				count_50K := 0;
				ck_512Hz <= not ck_512Hz;
			end if;
		end if;
	end process;
	
	-- 512Hz counter to select digit and register output
	process (reset, ck_512Hz)
	begin
		if reset='1' then
			dig_selection <= (others => '0'); -- Initialize to 00
			an <= (others => '0'); -- Disable all displays
			dec_ddp <= (others => '1');
		elsif (ck_512Hz'event and ck_512Hz='1') then
			dig_selection <= dig_selection + "01";
			an <= an_en;
			dec_ddp <= decoded_dig; 
		end if;
	end process;
		
	-- multiplexer for digit selection
    with dig_selection select
		selected_dig <=	d1 when "00",
					 			d2 when "01",
								d3 when "10",
								d4 when others;
	
	-- digit decoding
	with selected_dig (4 downto 1) select
	decoded_dig (7 downto 1) <=
		"0000001" when "0000", --0
		"1001111" when "0001", --1
		"0010010" when "0010", --2
		"0000110" when "0011", --3
		"1001100" when "0100", --4
		"0100100" when "0101", --5
		"0100000" when "0110", --6
		"0001111" when "0111", --7
		"0000000" when "1000", --8
		"0000100" when "1001", --9
		"0001000" when "1010", --A
		"1100000" when "1011", --b
		"0110001" when "1100", --C
		"1000010" when "1101", --d
		"0110000" when "1110", --E
		"0111000" when others; --F
	decoded_dig (0) <= selected_dig(0);
	
	-- digit decoding
	tmp_vec3 <= dig_selection & selected_dig(5);
	with (tmp_vec3) select
		an_en <=	"1110" when "001", -- digit 1 enabled
					"1101" when "011", -- digit 2 enabled
					"1011" when "101", -- digit 3 enabled
					"0111" when "111", -- digit 4 enabled
					"1111" when others; -- all digits disabled

end dio4_dspl_drv;