--
--  o circuito match implementa a resposta 2 da prova - T138
--
--  ESTE CIRCUITO FUNCIONA CORRETAMENTE, MORAES EM 23/11/2001 
--
library IEEE;
use IEEE.Std_Logic_1164.all;    
use IEEE.Std_Logic_unsigned.all;
   
entity match is
        port( ck, reset, din : in std_logic; 
          padrao : in std_logic_vector(3 downto 0);  
              vezes : out std_logic_vector(3 downto 0)
             );
end match;

architecture a1 of match is  
   signal word, vz : std_logic_vector(3 downto 0);
   signal cont : std_logic_vector(1 downto 0);        
begin  
        
    process(reset, ck)
    begin
        if reset = '1' then
            word<= (others=>'0');
        elsif ck'event and ck='1' then
            word<= din & word(3 downto 1);
        end if;
    end process;
    
        process(reset, ck)
    begin
        if reset = '1' then
            vz<= (others=>'0');
            cont <= (others=>'0');
        elsif ck'event and ck='1' then
            if word=padrao  then     
               cont <= cont + 1;
               if cont="00" then vz<=vz+1; end if;
            else  
               cont <= (others=>'0');
            end if;
        end if;
    end process;
    
    vezes <= vz;    
    
end a1;
 


--
--  outra implementação - ver provável diferenca com a outra simulaçao 
--
--   observar quando o padrão for 0011 e a sequencia 10011100100
--            simulação entre 480 e 600 ns
--
library IEEE;
use IEEE.Std_Logic_1164.all;    
use IEEE.Std_Logic_unsigned.all;
   
entity matchFSM is
        port( ck, reset, din : in std_logic; 
          padrao : in std_logic_vector(3 downto 0);  
              vezes : out std_logic_vector(3 downto 0)
             );
end matchFSM;

architecture a1 of matchFSM is  
   type STATE is  (S1, S2, S3, S4); 
   signal EA, PE : STATE ;       
   signal vz : std_logic_vector(3 downto 0);
begin  
        
    process(reset, ck)
    begin
        if reset = '1' then
            EA <= S1; 
            vz <= (others=>'0');
        elsif ck'event and ck='1' then
            EA <= PE;
            if EA=S4 and din=padrao(3) then  vz<=vz+1;  end if;            
        end if;
    end process;
 
    process(EA, din, padrao)
     begin
       case(EA) is
        when S1 => if din=padrao(0) then PE<=S2; else PE<=S1; end if;
        when S2 => if din=padrao(1) then PE<=S3; else PE<=S1; end if;
        when S3 => if din=padrao(2) then PE<=S4; else PE<=S1; end if;
        when S4 =>  PE<=S1; 
       end case;
    end process;
    
    vezes <= vz;    
    
end a1;      

------------------------------------------------------------------------------------
--
--      teste do match
------------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;   

entity match_tb is
end match_tb;

architecture TB_ARCHITECTURE of match_tb is

     
    signal ck, reset, din : std_logic;
    signal padrao, vezesCerto, vezesErrado : std_logic_vector(3 downto 0);
    
    constant vetor : std_logic_vector(0 to 31) := "11111111111101001001110010011000"; 
begin

    U1 : entity work.match
                port map (ck => ck, reset => reset, din => din, padrao => padrao,vezes => vezesCerto );

    U2 : entity work.matchFSM
                port map (ck => ck, reset => reset, din => din, padrao => padrao,vezes => vezesErrado );

    reset <= '1', '0' after 2 ns, '1' after 200 ns, '0' after 203 ns;
    padrao <= "1111", "0011" after 200 ns ;
                   
   -- gerador de clock
   process 
     variable cont : integer := 0;
    begin
        ck <= '0', '1' after 5 ns;
        din <= vetor(cont);
        cont := cont +1;
        if cont=32 then cont:=0; end if;
        wait for 10 ns;
   end process;     
           
         
end TB_ARCHITECTURE;