somador Project Status (03/18/2014 - 11:16:11) | |||
Project File: | somador4.xise | Parser Errors: | No Errors |
Module Name: | somador | Implementation State: | Programming File Generated |
Target Device: | xc3s1200e-4fg320 |
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No Errors |
Product Version: | ISE 13.2 |
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No Warnings |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of 4 input LUTs | 6 | 17,344 | 1% | ||
Number of occupied Slices | 3 | 8,672 | 1% | ||
Number of Slices containing only related logic | 3 | 3 | 100% | ||
Number of Slices containing unrelated logic | 0 | 3 | 0% | ||
Total Number of 4 input LUTs | 6 | 17,344 | 1% | ||
Number of bonded IOBs | 12 | 250 | 4% | ||
Average Fanout of Non-Clock Nets | 2.00 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Tue Mar 18 11:04:27 2014 | 0 | 0 | 0 | |
Translation Report | Current | Tue Mar 18 11:14:38 2014 | 0 | 0 | 0 | |
Map Report | Current | Tue Mar 18 11:14:58 2014 | 0 | 0 | 2 Infos (2 new) | |
Place and Route Report | Current | Tue Mar 18 11:15:02 2014 | 0 | 0 | 1 Info (1 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Tue Mar 18 11:15:29 2014 | 0 | 0 | 5 Infos (5 new) | |
Bitgen Report | Current | Tue Mar 18 11:16:01 2014 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Log File | Current | Tue Mar 18 11:16:11 2014 |