somador Project Status (03/18/2014 - 11:16:11)
Project File: somador4.xise Parser Errors: No Errors
Module Name: somador Implementation State: Programming File Generated
Target Device: xc3s1200e-4fg320
  • Errors:
No Errors
Product Version:ISE 13.2
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 6 17,344 1%  
Number of occupied Slices 3 8,672 1%  
    Number of Slices containing only related logic 3 3 100%  
    Number of Slices containing unrelated logic 0 3 0%  
Total Number of 4 input LUTs 6 17,344 1%  
Number of bonded IOBs 12 250 4%  
Average Fanout of Non-Clock Nets 2.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Mar 18 11:04:27 2014000
Translation ReportCurrentTue Mar 18 11:14:38 2014000
Map ReportCurrentTue Mar 18 11:14:58 2014002 Infos (2 new)
Place and Route ReportCurrentTue Mar 18 11:15:02 2014001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentTue Mar 18 11:15:29 2014005 Infos (5 new)
Bitgen ReportCurrentTue Mar 18 11:16:01 2014000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentTue Mar 18 11:16:11 2014

Date Generated: 03/18/2014 - 11:16:11