Universidade Católica do Rio Grande do Sul

CADENCE University Program Member


Created: March, 2007
Last Update: February, 2019


 

The teaching activities and research projects described below employ CADENCE design tools.

 

Computer Engineering Undergraduate courses:

  1. Microelectronics  (60-hour course) Introduction to MOS technology. MOS transistor theory. CMOS fabrication process. Electrical simulation. Basic cell design. Standard-cell design flow. Post-layout simulation. Students use Cadence products to learn Digital IC design and Verification.
    Layout tutorial (in Portuguese)
    Basic Standard Cell tutorial (in Portuguese)
  2. VLSI  (60-hour course) CAD tools. Main algorithms of CAD tools. Design techniques. Design of a VLSI circuit, from VHDL to layout. Students use Cadence products to design and verify the VLSI circuit.
  3. VLSI Design II  (60-hour course) Introduction to system level design techniques. Hardware-software codesign. Test of VLSI circuits (the IC is sent to the foundry in the previous course, and tested in this one).
  4. Test and systems reliability  (60-hour course) Introduction to hardware and software test. DFT - design for testability and BIST - Buit in self test. Redundancy techniques (TMR).

Computer Science Graduate courses:

  1. VLSI Design  (30-hour course) Introduction to MOS technology. MOS transistor theory. CMOS fabrication process. Electrical simulation. Basic cell design. Standard-cell design flow. Post-layout simulation. Students use Cadence products to learn Digital IC and Custom IC design and verification.
  2. Digital and Embedded Systems   (30-hour course)Introduction to embedded systems and embedded system design. High-level specification of software and hardware of embedded systems. Verification of complex systems. Code coverage. Assertion based verification.
  3. Non-synchronous Digital Circuits and  Systems  (30-hour course) Introduction to synchronous and asynchronous circuits and systems. Synchronization problems in digital systems. Asynchronous design techniques. Asynchronous design tools.

Publications that mention the use of Cadence tools:

  1. A processor for IoT applications: An assessment of design space and trade-offs
    Microprocessors and Microsystems , v. 42, p.156-164, 2016
    JOHANN FILHO, S. ; MOREIRA, M. T. ; HECK, L. S. ; CALAZANS, N. L. V. ; HESSEL, F. P.
  2. Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling Applications
    In: SBCCI , 2016, 6p.
    BORTOLON, F. ; GIBILUKA, M. ; JOHANN FILHO, S. ; BAMPI, S. ; CALAZANS, N. L. V. ; HESSEL, F. P. ; MOREIRA, M. T.
  3. Blade - A Timing Violation Resilient Asynchronous Template
    In: International Symposium on Asynchronous Circuits and Systems (ASYNC) , 2015
    Hand, D. , Moreira, M. T. , Huang, H. H. , Chen, D. , Butzke, F. , Li, Z. , Gibiluka, M. , Breuer, M. , Calazans, N. L. V. , Beerel, P. A.
  4. A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies
    In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , 2015
    Singhvi, A. , Moreira, M. T. , Tadros, R. , Calazans, N. L. V. , Beerel, P. A.
  5. SDDS-NCL design: Analysis of supply voltage scaling
    In: SBCCI , 2015
    Ricardo A. Guazzelli; Fernando G. Moraes; Ney L. V. Calazans; Matheus T. Moreira
  6. Proposal of an Exploration of Asynchronous Circuits Templates and their Applications
    FACIN Technical Report , 2014
    M. T. Moreira and N. L. V. Calazans
  7. Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
    In: International Symposium on Asynchronous Circuits and Systems (ASYNC) , 2014
    Matheus Moreira; Augusto Neutzling; Mayler Martins; Andr?Reis; Renato Ribas; Ney Calazans
  8. A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design
    In: International Symposium on Asynchronous Circuits and Systems (ASYNC) , 2014
    Matheus Trevisan Moreira; Michel Evandro Arendt; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans
  9. Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis
    In: Great Lakes Symposium on VLSI (GLSVLSI) , 2014, 6p.
    Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck; Ney Laert Vilar Calazans
  10. Design of NCL Gates with the ASCEnD Flow
    In: LASCAS , 2013
    M. T. Moreira, C. H. M. Oliveira, R. C. Porto and N. L. V. Calazans
  11. A 65nm standard cell set and flow dedicated to automated asynchronous circuits design
    In: SOCC , 2011, pp. 99-104.
    M. T. Moreira, B. S. Oliveira, J. J. H. Pontes, N. L. V. Calazans
  12. Design and Implementation of a Standard Cell Library for Building Asynchronous ASICs
    End of Term Work , Computer Engineering, PUCRS, 2011
    M. T. Moreira

Chip Designs:


   

Main Research Projects (funded by government research agencies):


Contact Points: Prof. Fernando Gehm Moraes and Prof. Ney Laert Vilar Calazans


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