X10GIGA
- is a collaborative effort between PUCRS (through the GAPH
Research Group), TERACOM Telemática Ltd, a Brazilian telecom
equipment enterprise, the UFC (through the LESC Laboratory) and the
Atlântico Institute (in Fortaleza, Ceará). The main objective of the
project is to develop a transponder capable of transmitting SDH
frames and Gigabit Ethernet packets over Optical Transport Networks
(OTNs) with long-distance optical links. The transponder will be
used as a complementary equipment or integrated within TERACOM
products, aggregating functionalities that today depend on
other manufacturers' equipments. The three scientific organizations
(GAPH/LESC/Atlântico Institute) will contribute to develop an
dominate technologies like Gigabit Ethernet (GbE) and SDH signal
transport functions over OTN networks implemented in FPGAs, 10Gbps
optical transceivers with integrated power amplifiers and OTN
network management embedded software. The project started in March 2007 and has a duration of
24 months. It is co-financed by FINEP Brazilian research funding
agency and TERACOM. [General Coordinator:
Fernando Gehm Moraes]
TeTHA
- is a collaborative effort between PUCRS (through the GAPH Research
Group) and TERACOM Telemática Ltd, a Brazilian telecom equipment
enterprise. The main objective of the project is to develop
Intellectual Property cores (IP cores) to aid in the implementation
of hardware modules for transporting Internet Protocol (IP) traffic
on high speed networks that employ Ethernet in the lower layers of
the communication protocol stack. The developed IP cores are to be
immediately used in TERACOM products, increasing the competitivity
of the enterprise in internal and world markets. The IP cores will
comprise modules initially prototyped in FPGAs, followed by the
generation of an IC layout mask set for ASIC fabrication. The
project started in January 2006 and has a duration of 18 months. It
is co-financed by the FINEP Brazilian research funding agency and
TERACOM. [General Coordinator:
Ney Laert Vilar Calazans]
Brazil_IP - is a collaborative effort of Brazilian
institutions to create a distributed network of integrated circuit
(IC) design centers capable of delivering
OCP-IP compliant Intellectual Property (IP
cores). The mission of Brazil IP are twofold. In the short run, it
aims at increasing the country expertise on designing world-class
IC's by exposing the participating centers to real-world design
practices and evaluation. In the long-run, it seeks to enable the
conditions for the establishment of local Design Houses (DH's)
capable of competing in the international IP market. The project
involves 8 Brazilian university research groups and a research
center. The project started in February 2003 and has a duration of 4
years. [General Coordinator: Edna Natividade da Silva Barros,
Local Coordinator:
Ney Laert Vilar Calazans]
RICHA - Hardware Intra-chip
Interconnection Networks - The RICHA project has two strategic
objectives: development of intra-chip standard interfaces for
intellectual property cores (IP cores) and developing techniques for
intra-chip IP cores interconnection. Specific Project Goals(short term, 6-9 months): (1) Dominate the OCP interface standard.
Objective: making IP cores compatible for interconnection. (2)
Development and prototyping of a single processor system inside a
programmable FPGA device, using bus interconnection between
processor, memory and peripherals. Objective: make available as an
IP core the selected embedded processor, together with its
arbitration and communication mechanisms. (3) Research and
development of intra-chip networks (network-on-chip or NOC) and
intra-chip routing nodes with which the network is built. Objective:
make available an experimental framework for investigating
intra-chip networks. (long term, 15-21 months): (4) Development of
an intra-chip multiprocessing system implemented in an FPGA device,
using bus-based interconnection. Objective: research the limitations
imposed by bus-based IP cores interconnection, to serve as a
reference for evaluation of NOCs. (5) Prototyping a simple
NOC in FPGA devices, together with the performance evaluation in
terms of area, speed and latency. Objective: determine architectural
bottlenecks and trade-off routing strategies and buffering in these
intra-chip interconnection architectures. (6)implement
different NOC topologies and propose a tool for user-parameterizable
NOCs construction. (7) performance evaluation of the implemented
NOCs. This project is funded by the CNPq, started
in October 2003 and has a duration of 2 years. [Coordinator:
Fernando
Gehm Moraes]
PRATA (Phase II) - This is a research project partially
funded by the CNPq and FAKERS Brazilian funding agencies to accompany
and dominate the state of the art in Systems on Chip (SoCs) design
and prototyping, using hardware/software codesign techniques and employing
reconfigurable systems. [Coordinator: Ney Laert Vilar
Calazans]
APSI - this research project proposes
to implement
a methodology, aided by a set of tools, to the specification and design
of multi-language heterogeneous embedded systems on chip. This methodology
is based on the separation between the system behavior (functionality) and
its communication interface. Target architectures are composed by a set of processor
cores and FPGAs boards integrated in a single chip, applied to the
voice encoding / decoding applications [Coordinator: Fabiano Passuelo Hessel]
LIBRARY FREE INTEGRATED CIRCUIT DESIGN FOR SUBMICRON
TECHNOLOGIES (KIT) - This project concentrates the research effort
in low level synthesis, specially by improving the current
state-of-the-art in this field, developing strategies for library
free mapping, virtual libraries, automatic layout synthesis
for submicron technologies and performance optimization. This
research is partially funded by the European Community as a KIT
(Keep-in-Touch) Project (EC)
[Coordinator: Fernando Gehm Moraes]
PROTOTYPING, VERIFICATION AND TEST OF ELECTRONIC SYSTEMS IN SILICON - (under construction) [Local Coordinator: Fernando Gehm Moraes]