--------------------------------------------------
--+ Expansion Permutation
--------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity E_box is 
	port (entrada : in std_logic_vector(1 to 32);
		saida : out std_logic_vector(1 to 48));
end E_box;

architecture E_box of E_box is
begin
	saida(1)<=entrada(32);
	saida(2 to 6)<=entrada(1 to 5);
	saida(7 to 8)<=entrada(4 to 5);
	saida(9 to 12)<=entrada(6 to 9);
	saida(13 to 14)<=entrada(8 to 9);
	saida(15 to 18)<=entrada(10 to 13);
	saida(19 to 20)<=entrada(12 to 13);
	saida(21 to 24)<=entrada(14 to 17);
	saida(25 to 26)<=entrada(16 to 17);
	saida(27 to 30)<=entrada(18 to 21);
	saida(31 to 32)<=entrada(20 to 21);
	saida(33 to 36)<=entrada(22 to 25);
	saida(37 to 38)<=entrada(24 to 25);
	saida(39 to 42)<=entrada(26 to 29);
	saida(43 to 44)<=entrada(28 to 29);
	saida(45 to 47)<=entrada(30 to 32);
	saida(48)<=entrada(1);

end E_box;

--------------------------------------------------
--+ Permutation Box
--------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity P_box is 
	port (entrada : in std_logic_vector(1 to 32);
		saida : out std_logic_vector(1 to 32));
end P_box;

architecture P_box of P_box is
begin
	saida<=
		entrada(16)&
		entrada(7)&
		entrada(20)&
		entrada(21)&
		entrada(29)&
		entrada(12)&
		entrada(28)&
		entrada(17)&
		entrada(1)&
		entrada(15)&
		entrada(23)&
		entrada(26)&
		entrada(5)&
		entrada(18)&
		entrada(31)&
		entrada(10)&
		entrada(2)&
		entrada(8)&
		entrada(24)&
		entrada(14)&
		entrada(32)&
		entrada(27)&
		entrada(3)&
		entrada(9)&
		entrada(19)&
		entrada(13)&
		entrada(30)&
		entrada(6)&
		entrada(22)&
		entrada(11)&
		entrada(4)&
		entrada(25);

end P_box;

library IEEE;
use IEEE.std_logic_1164.all;

entity round is
	port(
		clk,rst,
		strIn, vIn : in std_logic;
		strOut, vOut: out std_logic;
		
		textIn: in std_logic_vector(1 to 64);
		keyIn : in std_logic_vector(1 to 48);		
		textOut: out std_logic_vector(1 to 64)
		
	);
end round;

architecture round of round is
	signal subKey: std_logic_vector(1 to 48);
	signal data : std_logic_vector(1 to 64);
	
	signal entradaPbox, saidaPbox : std_logic_vector(1 to 32);
	signal saidaEbox, entradaSbox : std_logic_vector(1 to 48);
begin

	ebox: entity work.E_box
		port map(
			entrada=> data(33 to 64),
			saida=> saidaEbox
		);
		
	sbox: entity work.S_box
		port map(
			entrada=> entradaSbox,
			saida=> entradaPbox
		);
		
	pbox: entity work.P_box
		port map(
			entrada=> entradaPbox,
			saida=> saidaPbox
		);
			
	entradaSbox <= subkey xor saidaEbox;
	textOut <= data(33 to 64) & (data(1 to 32) xor saidaPbox);

	process(clk)
	begin
		if(clk'event and clk = '1')then
			if(rst = '1')then
				subkey <= (others=>'0');
				data <= (others=>'0');
				vOut <= '0';
				strOut <= '0';
			else
				data <= textin;				
				strOut <= strIn;
				vOut <= vIn;
				if(strIn = '1')then
					subkey <= keyIn;					
				end if;
			end if;		
		end if;
	end process;
	
end round;
