-------------------------------------------------------------------------
--  TOP CPU PROCESSOR SIMULATION TESTBENCH
-------------------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;          

entity CPU_tb is
end CPU_tb;

architecture cpu_tb of cpu_tb is
  signal clock, reset, selUSER, resetCPU, ceCPU, rwCPU, bwCPU,
            ceUSER, rwUSER, bwUSER : std_logic := '0';      	  
  signal addressUSER, dataUSER, addressCPU, data_outRAM, 
            data_outCPU : std_logic_vector(31 downto 0); 
begin

  	top: entity work.MIPS_S_withBRAMs port map (clock=>clock, 
            reset=>reset, selUSER=>selUSER, resetCPU=>resetCPU,
            addressUSER=>addressUSER, ceUSER=>ceUSER, rwUSER=>rwUSER,
            bwUSER=>bwUSER, dataUSER=>dataUSER,
            data_outRAM=>data_outRAM, ceCPU=>ceCPU, rwCPU=>rwCPU,
            bwCPU=>bwCPU, addressCPU=>addressCPU, data_outCPU=>data_outCPU
        );

	clock <= not clock after 5 ns;

	reset <= '1', '0' after 40 ns;       

    selUSER <= '0';
	
	ceUSER <= '0'; rwUSER <='0'; bwUSER <= '0';

	addressUSER <= (others=>'0');

	dataUSER <= (others=>'0');

end cpu_tb;
