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-- Company: 
-- Engineer: 
-- 
-- Create Date: 28.11.2021 13:20:47
-- Design Name: 
-- Module Name: top - top
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top_counts is
    Port ( clock :      in STD_LOGIC;
           reset :      in STD_LOGIC;
           hold_in :    in STD_LOGIC;
           hold_out :   out STD_LOGIC;
           selUSER :    in STD_LOGIC;
           dec_ddp :    out STD_LOGIC_VECTOR (7 downto 0);
           an :         out STD_LOGIC_VECTOR (7 downto 0));
end top_counts;

architecture top_counts of top_counts is
  signal ceUSER, rwUSER, bwUSER, resetCPU, ceCPU, rwCPU, bwCPU : std_logic := '0';      	  
  signal addressUSER, dataUSER, data_outCPU, 
            data_outRAM, addressCPU : std_logic_vector(31 downto 0); 
  signal d8, d7, d6, d5, d4, d3, d2, d1 : std_logic_vector(5 downto 0);
  signal hundreds, tens, units_s, tenths : std_logic_vector(3 downto 0);
  

begin

    Inst_MIPS_S_withBRAMs:
        entity work.MIPS_S_withBRAMs  port map(clock=>clock, reset=>reset,
			hold_in=>hold_in, hold_out=>hold_out,
            selUSER=>selUSER, ceUSER=>ceUSER, rwUSER=>ceUSER, bwUSER=>bwUSER,
            resetCPU=>resetCPU, addressUSER=>addressUSER, dataUSER=>dataUSER,
            data_outRAM=>data_outRAM, ceCPU=>ceCPU, rwCPU=>rwCPU, bwCPU=>bwCPU,
			addressCPU=>addressCPU, data_outCPU=>data_outCPU
			);

	Inst_Perif:
	   entity work.count_4BCDdigs port map( clock=>clock, reset=>resetCPU,
           addressCPU=>addressCPU, ce=>ceCPU, rw=>rwCPU, data_outCPU=>data_outCPU,
           hundreds=>hundreds, tens=>tens, units_s=>units_s, tenths=>tenths);

    -- Unused input signal to MIPS_S_withBRAMs are zeroed here
    addressUSER <= (others=>'0');
    dataUSER    <= (others=>'0');
    ceUSER      <= '0';
    rwUSER      <= '0';
    bwUSER      <= '0';

    -- Preparing data for the displays
    d8 <= "000000";
    d7 <= "000000";
    d6 <= "000000";
    d5 <= "000000";
    d4 <= '1' & hundreds & '1';
    d3 <= '1' & tens & '1';
    d2 <= '1' & units_s & '0';
    d1 <= '1' & tenths & '1';
	
	Inst_DisplDrv:
	   entity work.dspl_drv_8dig port map(clock=>clock, reset=>reset,
		d8=>d8, d7=>d7, d6=>d6, d5=>d5, d4=>d4, d3=>d3, d2=>d2, d1=>d1,
		an=>an, dec_ddp=>dec_ddp);

end top_counts;
