-------------------------------------------------------------------------
--  TOP CPU PROCESSOR SIMULATION TESTBENCH
-------------------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;          

entity counts_tb is
end counts_tb;

architecture counts_tb of counts_tb is
  signal clock, reset, selUSER : std_logic :='0';      	  
  signal an: std_logic_vector(7 downto 0);
  signal dec_ddp: std_logic_vector(7 downto 0);
  
begin
	inst_top_counts:
		entity work.top_counts
			port map (clock=>clock, reset=>reset, selUSER=>selUSER, an=>an, dec_ddp=>dec_ddp);
	  
	selUSER <= '0';

	reset <='1', '0' after 120 ns;       -- generates the reset signal 

	clock <= not clock  after 5 ns;

end counts_tb;