This folder contains the files used to implement a simple output only peripheral to couple with the MIPS_S_withBRAMs system.

The peripheral is basically a set of four 4-bit registers mapped to specific addresses on the MIPS_S memory map (0x10008000, 0x10008001, 0x10008002, and 0x10008003). There is also an address decoding logic that sniffs the address and control signals of the MIPS_S for writings to the registers, which outputs are in turn connected to the displays of the Nexys-7 board through a display driver circuit. 

Additionally, there is a control input (called hold_in) that produces a hold on the MIPS_S running the software that produces the timer values. This input is connected to the down push-button (BTND) of the Nexys-7 board. While the user presses this button the processor is in the Shold state. When the button is released the software proceeds and the times resumes its counting behavior. When the MIPS_S is in the Shold state, the status output signal is set to '1' and the rightmost led of the Nexys-7 board lights up to announce this.

The up push-button (BTNU), on the other hand, is connected to the reset of the system. Pressing it restarts the timer at 000.0.

This structure enables the software running on the MIPS_S to implement a counter that starts at 000.0s and counts tenths of seconds until it arrives at 999.9s, when the counter stops.

It is not adequate to simulate the complete execution of the system without modifying the counting of clocks, fo it would take too long.