Author: 				Ney Laert Vilar Calazans
Date of last update:	20/10/2022

Title: 					Description of the MIPS_S-withBRAMs System

This file describes the current status of the computational system mentioned in the title, MIPS_S-withBRAMs.

The system comprises a 32-bit processor that implements a subset of the MIPS-2000 instruction set architecture (ISA) and two memories built with Series 7 Xilinx FPGAs BRAMs. The memories serve to implement a Harvard processor organization, including an instruction memory and a data memory. Under the point of view of assembly programming, the instruction memory starts at the address 0x00400000 and the data memory starts at the address 0x10010000. Although the memories are physically separated, they share a same address space.

The system is integrated as a general purpose computational system, developed to allow learning computer architecture, computer organization and assembly language programming concepts.

Memories are quite small, with only 2Kbytes for instructions and 8Kbytes for data.

The current state of development is:
1) Simulation is enabled, as can be verified by running the two example programs available in folders .\DistribFiles\Asm-C\soma_vet_noPerif and .\DistribFiles\Asm-C\soma_vet-wchecking_noPerif. 
	- soma_vet_noPerif - a simple program that adds each element of two vectors V1 and V2 and stores the result in a vector V3. All vector have the same size, 11 elements. 
	- soma_vet-wchecking_noPerif - does exactly the same process as soma_vet_noPerif, but after each data writing operation, it reads the value from the data memory and compares with the value just written. This enables to see that the processor correctly reads and writes to the data memory.

2) The system is also prototypable. See example in folder .\DistribFiles\Asm-C\count_s_Perif
	- count_s_Perif - contains an example that work fine in hardware in the new version of the MIPS_S-withBRAMs. It produces a timer that is controlled by assembly software and starts with 000.0s and counts tenths of seconds, stopping after arriving at 999.9 seconds. The MIPS_S-withBRAMs system is coupled to a write-only peripheral (written by the software running in the MIPS_S processor), which is in turn coupled to four 7-segment displays in the Nexys-7 board from Digilent, using a display driver furnished with the distribution files.
	
3) There is a new control signal, called hold_in, that suspends momentarily the execution of instructions by the MIPS_S processor, while keeping everything else in place in registers and memory. This signal can be used externally to provide a means to have access to the data memory to read or write data blocks from or to it without interference. This is a way to provide some primitive direct memory access mechanism for external peripherals.

4) The MIPS_S-withBRAMs system has an interface that allows the interaction between it and external modules for reading or writing to its memory. There are documents available in folder .\DistribFiles\docs that explain the basic steps for using the system for hardware simulation and prototyping. A task that is yet to be accomplished comprises producing an example application of a system that not only reads but also writes data to the memory. Maybe it will be necessary to improve the system interface before developing a really useful example.