-------------------------------------------------------------------------------
--
-- Title       : Test Bench for the fibonacciero Hw
-- Design      : fibonacciero
-- Author      : Ney Calazans
-- Company     : PUCRS - School of Technology
--
-------------------------------------------------------------------------------
--
-- Description : Test Bench for fibonacciero_tb
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fibonacciero_tb is
end fibonacciero_tb;

architecture fibonacciero_tb of fibonacciero_tb is
	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal clock : std_logic:='0';
	signal reset : std_logic;
	signal anda_para : std_logic;
	signal nro_elementos : std_logic_vector(7 downto 0);
	-- Observed signals - signals mapped to the output ports of tested entity
	signal saida : std_logic_vector(7 downto 0);


begin

	-- Unit Under Test port map
	UUT : entity work.fibonacciero
		port map (
			clock => clock,
			reset => reset,
			anda_para => anda_para,
			nro_elementos => nro_elementos,
			saida => saida
		);

	process
	begin		
		wait for 10ns ;
		clock <= not clock;
	end process;

	reset <= '1', '0' after 18ns,'1' after 320ns, '0' after 329ns,
	'1' after 430ns, '0' after 439ns; 
	
	anda_para <= '1', '0' after 115ns, '1' after 135ns;
	
	nro_elementos <= x"0A", x"03" after 290ns, x"00" after 430ns;

end fibonacciero_tb;
