----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 24.06.2021 17:08:03
-- Design Name: 
-- Module Name: debounce_use_test_tb - debounce_use_test_tb
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity debounce_use_test_tb is
end debounce_use_test_tb;

architecture debounce_use_test_tb of debounce_use_test_tb is
signal clock : std_logic :='1';
signal reset, button, led : std_logic;
begin

inst_deb_test: 
    entity work.debounce_use_test 
    port map (  reset=>reset, clock=>clock, 
                button=>button, led=>led
             );

    clock <= not clock after 5ns; 
    reset <= '1', '0' after 3ns;
    
    button <= '0', '1' after 95ns, '0' after 150_000_005ns, '1' after 1_450_000_005ns, '0' after 1_600_000_005ns;

end debounce_use_test_tb;
