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-- Company: 
-- Engineer: 
-- 
-- Create Date: 24.06.2021 07:26:42
-- Design Name: 
-- Module Name: debounce_use_test - debounce_use_test
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity debounce_use_test is
    port ( reset, clock, button : in std_logic;
           led                  : out std_logic
         );
end debounce_use_test;

architecture debounce_use_test of debounce_use_test is
signal reset_N, led_int, tff_input, button_debounced : std_logic;

begin
    reset_N <= not reset;   -- inverta o reset para fazer ele ativo em '0',
                            --  como esperado pelo debounce
    
deb_inst:
    entity work.debounce 
    port map (reset_N=>reset_N, clock => clock, key => button, debkey=>button_debounced);

t_FF:   -- processo que implementa um flip-flop T ativado por button_debounced com chip enable
    process (reset, clock)
    begin
        if reset = '1'
        then led_int <= '0';
        elsif clock'event and clock='1' then
            if button_debounced = '1'
            then led_int <= tff_input;
            end if;
        end if;  
    end process;
    
    tff_input <= not led_int; 
    led <=led_int;
     
end debounce_use_test;
