Ney Calazans Publications (Sorted by Subject)

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In this classification, a publication may appear in one or more topics. Inside each topic, publications are ordered in descending order of publication date.

Asynchronous (Clockless) and GALS Circuits

Networks on Chip

Computing Systems, specially MPSoCs

Reconfigurable Systems

Fast Prototyping of Digital Circuits

Telecom Digital Systems

Electronic Design Automation Tools

Educational Resources

Applications and Other Subjects

Asynchronous (Clockless) and GALS Circuits

NUNES, W. A.; SARTORI, M. L. L.; CALAZANS, N. L. V. Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design. In: Simp�sio Brasileiro de Concep��o de Circuitos e Sistemas Integrados (SBCCI), Pelotas, 2022. Accepted for publication, final version inpreparation.

WUERDIG, R. N; SARTORI, M. L. L.; ABREU, B.; BAMPI, S.; CALAZANS, N. L. V. Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers. In: 2022 IEEE International Symposium on Circuits and Systems (ISCAS'22), Austin(TX), May 2022.

CALAZANS, N. L. V.; RODOLFO, T. A.; SARTORI, M. L. L. Robust and Energy-Efficient Hardware:The Case for Asynchronous Design. Journal of Integrated Circuits and Systems (JICS), 16(2), September 2021. pp.1-11.

RODOLFO, T. A.; SARTORI, M. L. L.; MOREIRA, M. T.; CALAZANS, N. L. V. Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. In: 2021 IEEE International Symposium on Circuits and Systems (ISCAS'21), Daegu, May 2021. 5pp.

BESKOW, A. L. Exhaustive and Genetic Flexible Approaches to Transistor Sizing of CMOS Gates. End of Term Work. Computer Engineering - PUCRS, December 2020. 64p. (Presented and approved. Advisor: Ney Laert Vilar Calazans, Co-Advisor: Marcos Luiggi Lemos Sartori).

SARTORI, M. L. L.; MOREIRA, M. T.; CALAZANS, N. L. V. A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow. In: 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'20), [Snowbird], 2020. pp. 3-10.

SARTORI, M. L. L.; WUERDIG, R. N.; MOREIRA, M. T.; BAMPI, S.; CALAZANS, N. L. V. Leveraging QDI Robustness to Simplify the Design of IoT Circuits. In: IEEE International Symposium on Circuits and Systems (ISCAS'20), Sevilha. Oct. 2020. 4p. (online).

SUSIN, G. M. ASCEND-TSMC180-NCL: A Simple NCL Cell Library to Support Manufacturable QDI Designs. End of Term Work. Computer Engineering - PUCRS, December 2019. 108p. (Presented and approved. Advisor: Ney Laert Vilar Calazans, Co-Advisor: Marcos Luiggi Lemos Sartori).

SARTORI, M. L. L. PULSAR: Towards a Synthesis flow for QDI Circuits. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. August 2019. (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans, Co-Advisor: Matheus Trevisan Moreira).

SARTORI, M. L. L.; WUERDIG, R. N.; MOREIRA, M. T.; CALAZANS, N. L. V. Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools. In: 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'19), Hirosaki, 2019. pp. 114-123. Best Paper Award Nominee.

WUERDIG, R. N.; SARTORI, M. L. L.; CALAZANS, N. L. V. Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations. In: 10th IEEE Latin American Symposium on Circuits and Systems (LASCAS'19), Armenia, 2019. pp. 137-140.

GUAZZELLI, R. A.; MOREIRA, M. T.; CALAZANS, N. L. V.; LAU NETO, W. Asynchronous Digital Circuit and Data Transfer and Processing Method in Asynchronous Digital Circuit, 2018. Deposited Patent. Category: Process. Deposit Institution: INPI - Instituto Nacional da Propriedade Industrial. Country: Brazil. Nature: Invention Patent. Record Number: BR1020180023063. Deposit date: 02/02/2018. (In Portuguese)

MOREIRA, M. T.; BEEREL, P. A.; SARTORI, M. L. L.; CALAZANS, N. L. V. NCL Synthesis with Conventional EDA Tools: Technology Mapping and Optimization. IEEE Transactions on Circuits and Systems I - Regular Papers, 65(6), June 2018, pp. 1981-1993.

HECK, Guilherme. The Impact of Voltage Scaling over Delay Elements with Focus on Post-Silicon Tests. PhD Thesis, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2018. Scholarship Sponsor: CNPq (PNM). (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans).

SARTORI, M. L. L.; CALAZANS, N. L. V. Go Functional Model for a RISC-V Asynchronous Organization - ARV. In: IEEE International Conference on Electronics, Circuits and Systems (ICECS'17), Batumi, 2017. pp. 381-384.

HECK, L. S.; MOREIRA, M. T.; CALAZANS, N. L. V. Hardening C-elements Against Metastability. In: IEEE International Conference on Electronics, Circuits and Systems (ICECS'17), Batumi, 2017. pp. 314-317.

SARTORI, M. L. L. ARV: Towards an Asynchronous Implementation of the RISC-V Architecture. End of Term Work. Computer Engineering - PUCRS, July 2017. 57p. (Presented and approved. Advisor: Ney Laert Vilar Calazans).

GUAZZELLI, R. A.; LAU NETO, W.; MOREIRA, M. T.; CALAZANS, N. L. V. Sleep Convention Logic Isochronic Fork: an Analysis. In: 30th Symposium on Integrated Circuits and Systems Design (SBCCI'17), 2017. pp. 103-109.

GUAZZELLI, Ricardo Aquino. QDI Asynchronous Design and Voltage Scaling. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2017. 113p (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans). PLEASE READ THIS BEFORE DOWNLOADING!

GUAZZELLI, R. A.; MOREIRA, M. T.; CALAZANS, N. L. V. A Comparison of Asynchronous QDI Templates Using Static Logic. In: IEEE Latin American Symposium on Circuits and Systems, 2017 (LASCAS), Bariloche, February 2017. pp. 261-264.

SINGHVI, AJAY; MOREIRA, M. T.; TADROS, RAMY N.; CALAZANS, N. L. V.; BEEREL, P. A. A Fine-Grained, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits. ACM Journal on Emerging Technologies in Computing Systems, 13(2), pp. 1-23, January 2017.

HECK, G.; HECK, L. S.; MOREIRA, M. T.; MORAES, F. G.; CALAZANS, N. L. V. A new local clock generator for globally asynchronous locally synchronous MPSoCs. Analog Integrated Circuits and Signal Processing, 89(3), pp. 631-640, December 2016.

OLIVEIRA, C. H. M.; MOREIRA, M. T.; GUAZZELLI, RICARDO A.; CALAZANS, N. L. V. ASCEnD-FreePDK45: An Open Source Standard Cell Library for Asynchronous Design. In: 23rd IEEE International Conference on Electronics Circuits and Systems (ICECS), December 2016. pp. 652-655.

GIBILUKA, M.; MOREIRA, M. T.; LAU NETO, W.; CALAZANS, N. L. V. A Standard Cell Characterization Flow for Voltage Scaling Operation. In: Symposium on Integrated Circuits and Systems Design (SBCCI), 2016.

ZHANG, Y.; HECK, L. S.; MOREIRA, M. T.; ZAR, D. M.; BREUER, M.; CALAZANS, N. L. V.; BEEREL, P. A. Testable MUTEX Design. IEEE Transactions on Circuits and Systems. I, Regular Papers, 63(8), pp. 1188-1199, August 2016.

TADROS, R. N., HUA, W., GIBILUKA, M., MOREIRA, M. T., CALAZANS, N. L. V., BEEREL, P. A. Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. In: 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), Porto Alegre, May 2016, pp. 11-18.

GIBILUKA, Matheus. Analysis of Voltage Scaling Effects in the Design of Resilient Circuits. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2016. 103p. Scholarship Sponsor: CNPq (PNM). (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans).

MOREIRA, Matheus Trevisan. Asynchronous Circuits: Innovations in Components, Cell Libraries and Design Templates. PhD Thesis, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. January 2016. 276p. Scholarship Sponsor: CNPq (PNM). (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans, Co-Advisor: Peter Beerel, University of Southern California).

TADROS, RAMY N.; HUA, WEIZHE; MOREIRA, MATHEUS T.; CALAZANS, NEY L. V.; BEEREL, PETER A. A Low Power, Low Area Error Detecting Latch for Resilient Architectures in 28nm FDSOI. IEEE Transactions on Circuits and Systems II: Express Briefs, 63(9), pp. 858-862, 2016.

OLIVEIRA, C. H. M. ASCEnD-FreePDK45: Design and Implementation of an Open Access Cell Library for Asynchronous Circuits. End of Term Work. Computer Engineering - PUCRS, 2015. 75p. (Presented and approved. Advisor: Matheus Trevisan Moreira, Co-Advisor: Ney Laert Vilar Calazans) (In Portuguese)

GIBILUKA, M.; MOREIRA, M. T.; CALAZANS, N. L. V. A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. In: 18th EUROMICRO Conference on Digital System Design, 2015, Funchal. DSD'15, 2015. pp. 79-86.

GUAZZELLI, R. ; MORAES, F. G. ; CALAZANS, N. L. V. ; MOREIRA, M. T. SDDS-NCL Design: Analysis of Supply Voltage Scaling. In: 28th Symposium on Integrated Circuits and Systems Design, 2015, Salvador. SBCCI'15, 2015. pp. 2-8.

BEEREL, P. A., CALAZANS, N. L. V. A Path Towards Average-Case Silicon via Asynchronous Resilient Bundled-data Design. In: 22nd European Conference on Circuit Theory and Design (ECCTD'15). Trondheim, Aug 2015. 4p.

SINGHVI, A., MOREIRA, M. T., TADROS, R. N., BEEREL, P. A., CALAZANS, N. L. V. A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies. In: International Symposium on VLSI (ISVLSI'15), Montpellier, 2015.

HAND, D., MOREIRA, M. T., HUANG, H., CHEN, D., BUTZKE, F., LI, Z., GIBILUKA, M., BREUER, M., CALAZANS, N. L. V., BEEREL, P. A. Blade - A Timing Violation Resilient Asynchronous Template. In: 21st IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'15). May 2015, pp. 21-28.

ZHANG, Y., HECK, L. S., MOREIRA, M. T., ZAR, D. M., BREUER, M., CALAZANS, N. L. V., BEEREL, P. A. Design and Analysis of Testable Mutual Exclusion Elements. In: 21st IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'15). May 2015, pp. 124-131.

HAND, D., HUANG, H., CHENG, B., ZHANG, Y., MOREIRA, M. T., BREUER, M., CALAZANS, N. L. V., BEEREL, P. A. Performance Optimization and Analysis of Blade Designs Under Delay Variability. In: 21st IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'15). May 2015, pp. 61-68.

MOREIRA, M. T., ARENDT, M. E., MORAES, F. G., CALAZANS, N. L. V. Static Differential NCL Gates: Towards Low Power. IEEE Transactions on Circuits and Systems. II, Express Briefs, 62(6), pp. 563-567, Jun. 2015.

HECK, G., HECK, L. S., MOREIRA, M. T., MORAES, F. G., CALAZANS, N. L. V. A Digitally Controlled Oscillator for Fine-Grained Local Clock Generators in MPSoCs. In: VI Latin American Symposium on Circuits & Systems (LASCAS'15), 2015. 4 p.

GIBILUKA, M., MOREIRA, M. T., MORAES, F. G., CALAZANS, N. L. V. BAT-Hermes: A Transition-Signaling Bundled-Data NoC Router. In: VI Latin American Symposium on Circuits & Systems (LASCAS'15), 2015. 4 p.

MOREIRA, M. T.; HAND, D.; BEEREL, P. A.; CALAZANS, N. L. V. TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and Optimization. In: 16th International Symposium on Quality Electronic Design (ISQED'15), Santa Clara, 2015. pp. 379-383.

HECK, GUILHERME, HECK, LEANDRO S., SINGHVI, A., MOREIRA, M. T., BEEREL, P. A., CALAZANS, N. L.V. Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. In: 2015 28th International Conference on VLSI Design (VLSID'15), Bangalore, 2015, pp.321-326.

MOREIRA, Matheus T.; HECK, Leandro S.; HECK, Guilherme; GIBILUKA Matheus; CALAZANS, Ney Laert Vilar; MORAES, Fernando G. The YeAH NoC Router. PPGCC-PUCRS Technical Report Series, TR083, 4p. December, 2014.

MOREIRA, M. T.; TROJAN, G.; MORAES, F. G.; CALAZANS, N. L. V. Spatially Distributed Dual-Spacer Null Convention Logic Design. Journal of Low Power Electronics (Print), 10(3), September, 2014. pp. 313-320.

MOREIRA, M. T.; ARENDT, M.; ZIESEMER, A.; REIS, R.; CALAZANS, N. L. V. Automated Synthesis of Cell Libraries for Asynchronous Circuits. In: 27th Symposium on Integrated Circuits and Systems Design (SBCCI'14), 2014. pp. 183-188.

MOREIRA, M. T.; MORAES, F. G.; CALAZANS, N. L. V. Beware the Dynamic C-element. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Brief, 22(7), July, 2014. pp. 1644-1647.

MEDEIROS, Guilherme Espͭndola. Evolution of the LiChEn Tool for Characterization of Cells for the Design of Asynchronous Circuits. End of Term Work. Computer Engineering - PUCRS, 2014. 46p. (Presented and approved. Advisor: Ney Laert Vilar Calazans, Co-Advisor: Matheus Trevisan Moreira) (In Portuguese)

MOREIRA, M. T.; GUAZZELLI, R.; HECK, G.; CALAZANS, N. L. V. Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm Synthesis. In: 24th Great Lakes Symposium on VLSI (GLSVLSI'14), Houston, 2014, pp. 3-8.

ZIESEMER JR., A.; REIS, Ricardo Augusto da Luz; MOREIRA, M. T.; ARENDT, M. E.; CALAZANS, N. L. V. A Design Flow for Physical Synthesis of Digital Cells with ASTRAN. In: 24th Great Lakes Symposium on VLSI (GLSVLSI'14), Houston, 2014, pp. 245-246.

MOREIRA, M. T.; ARENDT, M. E.; GUAZZELLI, R.; CALAZANS, N. L. V. A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design. In: International Symposium on Asynchronous Circuits and Systems (ASYNC'14), Potsdam, 2014. pp. 93-100.

MOREIRA, M. T.; CALAZANS, N. L. V.; SILVA, A. N.; MARTINS, M. G. A.; REIS, A. I.; RIBAS, R. P. Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? In: International Symposium on Asynchronous Circuits and Systems (ASYNC'14), Potsdam, 2014, pp. 53-60.

MOREIRA, M. T., ARENDT, M. E., ZIESEMER JR., A., REIS, R. A. L., CALAZANS, N. L. V. Automated Synthesis of Cell Libraries for Semi-Custom Asynchronous Design. In: International Symposium on Asynchronous Circuits and Systems (ASYNC'14-Demos), 2014. pp. 49-50.

BUTZKE, F., MYERS, C., MOREIRA, M. T., CALAZANS, N. L. V. QDI Logic for Signaling Data Validity in Bundled-Data Design: A Kogge-Stone Case Study In: International Symposium on Asynchronous Circuits and Systems (ASYNC'14) - Fresh Ideas Workshop, Potsdam, 2014, pp. 40-41.

MOREIRA, M. T., CALAZANS, N. L. V. Quasi-Delay-Insensitive Return-to-One Design. In: Design, Automation & Test in Europe PhD Forum, March 2014, 2p.

MOREIRA, M. T.; PONTES, J. J. H.; CALAZANS, N. L. V. Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous Design. In: International Symposium on Quality Electronic Design (ISQED'14), March 2014, pp. 692-699.

GUAZZELLI, R.; HECK, G.; MOREIRA, M. T.; CALAZANS, N. L. V. Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough? In: 15th IEEE Latin-American Test Workshop (LATW'14), Fortaleza, March 2014, 5p.

MOREIRA, Matheus T.; CALAZANS, Ney Laert Vilar. Proposal of an Exploration of Asynchronous Circuits Templates and their Applications. PPGCC-PUCRS Technical Report Series, TR077, 47p. March, 2014.

ZIESEMER JR., A. ; REIS, Ricardo Augusto da Luz ; MOREIRA, M. T. ; ARENDT, M. E. ; CALAZANS, N. L. V. Automatic Layout Synthesis with ASTRAN Applied to Asynchronous Cells. In: 5th IEEE Latin American Symposium on Circuits and Systems (LASCAS'14), Santiago, February 2014, 4p.

GIBILUKA, Matheus. Design and Implementation of an Asynchronous NoC Router Using a Transition-Signaling Bundled-Data Protocol. End of Term Work. Computer Engineering - PUCRS, 2013. 110p. (Presented and approved. Advisor: Ney Laert Vilar Calazans)

MOREIRA, M. T., CALAZANS, N. L. V. Voltage Scaling on C-Elements: A Speed, Power and Energy Efficiency Analysis. In: 31st IEEE International Conference on Computer Design (ICCD'13), Asheville, 2013. pp. 329-334.

MOREIRA, M. T., OLIVEIRA, B. S., MORAES, F. G., CALAZANS, N. L. V. Charge Sharing Aware NCL Gates Design. In: 16th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13), New York, 2013. pp. 212-217.

MOREIRA, M. T., MAGALHAES, F. G., HESSEL, F. P., CALAZANS, N. L. V. BaBaNoC: An Asynchronous Network-on-Chip Described in Balsa. In: IEEE International Symposium on Rapid System Prototyping (RSP'13), Montreal, 2013. pp. 37-43.

MOREIRA, Matheus T.; MAGALHÃƒES, Felipe; GIBILUKA, Matheus; HESSEL, Fabiano P.; CALAZANS, Ney Laert Vilar. Power-Efficient Clockless Intrachip Communication Design with an Integrated High to Low Level Flow based on the Balsa Framework. PPGCC-PUCRS Technical Report Series, TR075, 15p. September, 2013.

MOREIRA, M. T., OLIVEIRA, C. H. M., Calazans, N. L. V., OST, L. C. LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries. In: 16th Euromicro Conference on Digital System Design (DSD'13), Santander, 2013.

PONTES, Julian Jos� Hilgemberg, Calazans, N. L. V., VIVET, P. H2A: A Hardened Asynchronous Network on Chip. In: 26th Symposium on Integrated Circuit and Systems Design (SBCCI'13), 2013. 6p.

MOREIRA, M. T.; MENEZES, C. H.; PORTO, R. C.; CALAZANS, N. L. V. NCL+: Return-to-One Null Convention Logic. In: IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'13), 2013, Columbus, OH, 2013. pp. 836-839.

MOREIRA, M. T., Calazans, N. L. V. Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD Flow. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI'13), Natal, 2013. 2p. PhD Forum Best Paper Award.

PONTES, J. J. H.; CALAZANS, N. L. V. ; VIVET, P. Parity Check for m-of-n Delay Insensitive Codes. In: 19th IEEE International On-Line Testing Symposium (IOLTS'13), Chania, 2013. pp. 157-162.

HECK, G., HECK, L. S., MOREIRA, M. T., MORAES, F. G., Calazans, N. L. V. A Fine-Grain Local Clock Generator Architecture to Enable Dynamic Frequency Scaling in MPSoCs. In: 28� Simp�sio Sul de Microeletr�nica (SIM'13), Porto Alegre, 2013. 4p.

MOREIRA, M. T., OLIVEIRA, C. H. M., Calazans, N. L. V. ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous Design. In: 28� Simp�sio Sul de Microeletr�nica (SIM'13), Porto Alegre, 2013. 4p.

HECK, Leandro Sehnem. Modeling and Design of a Local Clock Generator Based on DCO for GALS MPSoCs. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2013. Scholarship Sponsor: CNPq (PNM). (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans, Co-Advisor: C�sar Augusto Missio Marcon). (In Portuguese).

MOREIRA, M. T., MENEZES, C. H., PORTO, R. C., Calazans, Ney. Design of NCL Gates with the ASCEnD Flow. In: Fourth Latin American Symposium on Circuits and Systems (LASCAS'13), Cuzco, 2013. 6 p.

MOREIRA, M. T., CALAZANS, N. L. V. Electrical Characterization of a C-Element with LiChEn. In: IEEE International Conference on Electronics, Circuits, and Systems (ICECS'12), Sevilha, 2012, pp. 583-585. PhD Competition Award Winner.

MOREIRA, M. T., GUAZZELLI, R., CALAZANS, N. L. V. Return-to-One DIMS Logic on 4-phase m-of-n Asynchronous Circuits. In: IEEE International Conference on Electronics, Circuits, and Systems (ICECS'12), 2012, Sevilha, 2012, pp. 669-672.

PONTES, Julian Jos� Hilgemberg. Soft Error Mitigation in Asynchronous Networks on Chip. 2012. PhD Thesis, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. August 2012. 143p. Scholarship Sponsor: CNPq (PNM). (Presented and approved. Research Advisor: Ney Laert Vilar Calazans).

HECK, Guilherme. A GALS MPSoC Based on an Intrachip Network with Local Clock Generation. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. August 2012. 123p. Scholarship Sponsor: CNPq (PNM). (Presented and approved. Research Advisor: Ney Laert Vilar Calazans). (In Portuguese).

MOREIRA, M. T., GUAZZELLI, R., CALAZANS, N. L. V. Return-to-One Protocol for Reducing Static Power in QDI Circuits Employing m-of-n Codes. In: 25th Symposium on Integrated Circuit and Systems Design, SBCCI'12, 2012. 6p.

PONTES, J. J. H., CALAZANS, N. L. V., VIVET, P. Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects. In: 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'12), Lyngby, 2012, pp. 142-149.

MOREIRA, Matheus Trevisan. Contributions to the Design and Prototyping of GALS and Asynchronous Systems. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. April 2012. 79p. Scholarship Sponsor: CAPES. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans).

PONTES, J. J. H., CALAZANS, N. L. V., VIVET, P. An Accurate Single Event Upset Digital Design Flow for Reliable System Level Design. In: Design, Automation and Test in Europe, Dresden (DATE'12), 2012, pp. 224-229.

MOREIRA, M. T.; OLIVEIRA, B. S.; PONTES, J. J. H.; MORAES, F. G.; CALAZANS, N. L. V. Impact of C-Elements in Asynchronous Circuits. In: International Symposium on Quality Electronic Design, Santa Clara (ISQED'12), 2012, pp. 438-444.

HECK, G.; GUAZZELLI, R.; SOARES, R. I.; MORAES, F. G.; Calazans, N. L. V. HardNoC: A Platform to Validate Networks on Chip through FPGA Prototyping. In: VIII Southern Programmable Logic Conference (SPL'12), Bento Gon�alves, 2012, pp. 15 - 20.

SOARES, R. I., CALAZANS, N. L. V., MORAES, F. G., MAURINE, P., TORRES, L. A Robust Architectural Approach for Cryptographic Algorithms using GALS Pipelines. IEEE Design & Test of Computers, 28(5), 2011. pp. 62-71.

MOREIRA, Matheus T.; OLIVEIRA, Bruno; PONTES, Julian J. H.; CALAZANS, Ney Laert Vilar. Automated versus Manual Design of Asynchronous Circuits in DSM Technologies. PPGCC-PUCRS Technical Report Series, TR065, 15p. Juy, 2011.

SOARES, R. I., CALAZANS, N. L. V., LOMNE, V., DEHBAOUI, A., MAURINE, P., TORRES, L. A GALS Pipeline DES Architecture to Increase Robustness against CPA and CEMA Attacks. JICS - Journal of Integrated Circuits and Systems, vol. 6, Mar. 2011, pp. 25-34.

MOREIRA, M. T., OLIVEIRA, B. S., PONTES, J. J. H., MORAES, F. G., CALAZANS, N. L. V. Adapting a C-Element Design Flow for Low Power. In: IEEE International Conference on Electronics, Circuits, and Systems, Beirut (ICECS'11), 2011, pp. 45-48.

MOREIRA, M. T., OLIVEIRA, B. S., PONTES, J. J. H., CALAZANS, N. L. V. A 65nm Standard Cell Set and Flow Dedicated to Automated Asynchronous Circuits Design. In: 24th IEEE International SoC Conference (SoCC'11), 2011, pp. 99-104.

ROSA, T. R., GUINDANI, G., CARDOSO, D, CALAZANS, N. L. V.; MORAES, F. G. A Self-adaptable Distributed DFS Scheme for NoC-based MPSoCs. In: Symposium on Integrated Circuits and Systems Design (SBCCI'11), Sep. 2011, pp. 203-208.

SOARES, Rafael Iankowski. GALS Pipeline Architectures for Cryptography Robust to DPA and DEMA Attacks. 2010. PhD Thesis, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. November 2010. Scholarship Sponsor: CNPq (PNM). (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese).

PONTES, Julian Jos� Hilgemberg, MOREIRA, M. T., MORAES, F. G., CALAZANS, N. L. V. Hermes-AA - A 65nm Asynchronous NoC Router with Adaptive Routing. In: 23rd IEEE International SoC Conference (SOCC'10). IEEE Computer Society, Las Vegas, 2010, pp. 493-498.

PONTES, J. J. H., MOREIRA, M. T., MORAES, F. G., CALAZANS, N. L. V. Hermes-A - An Asynchronous NoC Router with Distributed Routing. In: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'10), LNCS volume 6448, Grenoble, 2010, pp. 150-159.

SOARES, R. I., CALAZANS, N. L. V., LOMNE, V., DEHBAOUI, A., MAURINE, P., TORRES, l. A GALS Pipeline DES Architecture to Increase Robustness against DPA and DEMA Attacks. In: Symposium on Integrated Circuits and Systems Design (SBCCI'10), S�o Paulo, 2010, pp. 115-120.

RODOLFO, Taciano Ares. An Exploration of the Design Space for Processors with Floating Point Point Hardware in FPGAs. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2010. 109p. Scholarship Sponsor: CNPq (PNM). (Presented and . Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

MOREIRA, Matheus Trevisan. Design and Implementation of a Standard Cell Library for Building Asynchronous ASICs. End of Term Work. Computer Engineering - PUCRS. December 2010. 139 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans)

TOFFOLO, Valter. A Clock Generator with Dynamic Frequency Scaling for Globally Asynchronous Locally Synchronous Systems. End of Term Work. Computer Engineering - PUCRS. December 2010. 72 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

SOARES, Rafael Iankowski, CALAZANS, Ney Laert Vilar, LOMNE, Victor, TORRES, Lionel, MAURINE, Philippe., ROBERT, Michel. Evaluating the Robustness of Secure Triple Track Logic through Prototyping. In: 21st Symposium on Integrated Circuits and Systems - SBCCI 2008, Gramado, 2008, pp. 193-198.

PONTES, Julian Jos� Hilgemberg, MOREIRA, Matheus Trevisan; SOARES, Rafael Iankowski; CALAZANS, Ney Laert Vilar. Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. In: IEEE Computer Society Annual Symposium on VLSI Design - ISVLSI 2008, Montpellier, April, 2008, pp. 347-352.

PONTES, Julian Jos� Hilgemberg. Design and Prototyping of Non-synchronous Interfaces and Intrachip Networks in FPGAs. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. February 2008. 120p. Scholarship Sponsor: CAPES. (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

PONTES, Julian Jos� Hilgemberg, SOARES, Rafael Iankowski, CARVALHO, Ewerson Luiz de Souza, MORAES, Fernando Gehm, CALAZANS, N. L. V. SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. In: XXV IEEE International Conference on Computer Design - ICCD 2007, Lake Tahoe, 2007, pp. 541-546.

Networks on Chip

MORENO, E. I., SANTOS, T. C. W., MARCON, C. A. M., MORAES, F. G., CALAZANS, N. L. V. MoNoC: A Monitored Network on Chip with Path Adaptation Mechanism. Journal of Systems Architecture (JSA), 60(10), November, 2014. pp. 783-795.

MORENO, E. I.;WEBBER, T.; MARCON, C. A. M.; MORAES, F. G.; CALAZANS, N. L. V. A Monitored NoC with Runtime Path Adaptation. In: IEEE International Symposium on Circuits and Systems (ISCAS'14), Melbourne, 2014. pp. 1965-1968 .

CARARA, E. A., CALAZANS, N. L. V., MORAES, F. G. Differentiated Communication Services for NoC-Based MPSoCs. IEEE Transactions on Computers (Special Issue on Networks on Chip), 63(3), March 2014, pp. 595-608.

SCHNEIDER, William. Systematic Evaluation of Intrachip Network. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2014. Scholarship Sponsor: CNPq (PNM). (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans). (In Portuguese)

SOUZA, Y. G.; MOREIRA, M. T.; BRAHM, L.; SANTOS, T. C. W.; Calazans, N. L. V.; MARCON, C�sar Augusto Missio. Lasio 3D NoC Vertical Links Serialization: Evaluation of Latency and Buffer Occupancy. In: 26th Symposium on Integrated Circuit and Systems Design (SBBCI'13), Curitiba, 2013. 6p.

PONTES, Julian Jos� Hilgemberg, Calazans, N. L. V., VIVET, P. H2A: A Hardened Asynchronous Network on Chip. In: 26th Symposium on Integrated Circuit and Systems Design (SBCCI'13), 2013. 6p.

PONTES, HJ. J. H.; CALAZANS, N. L. V. ; VIVET, P. Parity Check for m-of-n Delay Insensitive Codes. In: 19th IEEE International On-Line Testing Symposium (IOLTS'13), Chania, 2013. pp. 157-162.

SOUZA, Y. G., MOREIRA, M. T., SANTOS, T. C. W., CALAZANS, N. L. V., MARCON, C�sar Augusto Missio. TSV Multiplexing: A 3D NoC Occupancy Analysis. In: W5 3D Integration - Applications, Technology, Architecture, Design, Automation, and Test (W5'13), Grenoble, 2013.

SCHEMMER, Raffael Bottoli. An Infrastructure for the Generation and Evaluation of Hermes-G Intrachip Networks. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. August 2012. Scholarship Sponsor: CNPq (PNM). (Presented and approved. Research Advisor: Ney Laert Vilar Calazans). (In Portuguese).

MARCON, C. A. M.; CALAZANS, N. L. V.; MORENO, E. I.; MORAES, F. G.; HESSEL, F. P.; SUSIN, A. A. CAFES: A Framework for Intrachip Application Modeling and Communication Architecture Design. Journal of Parallel and Distributed Computing vol. 71, 2011, pp. 714-728.

MORENO, E.; MARCON, C. A. M.; CALAZANS, N. L. V.; MORAES, F. G. Arbitration and Routing Impact on NoC Design. In: IEEE International Symposium on Rapid System Prototyping (RSP'11), Karlsruhe, May 2011, pp. 193-198.

FERREIRA, Bruno Fin and HEINEN, Ismael Luͭs. HNPlus : A Network on Chip Prototyping Platform with a Generic Traffic Generation Scheme. End of Term Work. Computer Engineering - PUCRS. 2011. (Presented and approved. Advisor: Ney Laert Vilar Calazans)

TEDESCO, L. P., ROSA, T. R. da, CALAZANS, N. L. V., CLERMIDY, F., MORAES, F. G. Implementation and Evaluation of a Congestion Aware Routing Algorithm for Networks-on-Chip. In: Symposium on Integrated Circuits and Systems Design (SBCCI'10), S�o Paulo, 2010, pp. 91-96.

MORENO, Edson Ifarraguirre. Mapping and Communication Routes Adaptation in Networks on Chip. PhD Thesis, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. January 2010. Scholarship Sponsor: CNPq (PNM). (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans). (In Portuguese)

LANGE, Augusto, BOHRER, Vinicius P. & SILVA, Vinͭcius S. da. Adapting Systems to operate with On Chip Networks: Decoder M-JPEG/HERMES. End of Term Work. Computer Engineering - PUCRS. July 2010. 83 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

CARVALHO, Ewerson Luiz de Souza; MARCON, C�sar Augusto Missio; CALAZANS, N. L. V.; MORAES, F. G Evaluation of Static and Dynamic Task Mapping Algorithms in NoC-Based MPSoCs. In: International Symposium on System-on-Chip, 2009 (SOC'09), Tampere, 2009, pp. 87-90.

CARVALHO, Ewerson Luiz de Souza ; CALAZANS, N. L. V. ; MORAES, F. G. Investigating Runtime Task Mapping for NoC-based Multiprocessor SoCs. In: 17th IFIP/IEEE International Conference on Very Large Scale Integration, 2009, Florian�polis. VLSI-SoC, 2009. Paper 47, 6p.

CARARA, Everton Alceu ; CALAZANS, N. L. V. ; MORAES, F. G. Managing QoS Flows at Task Level in NoC-Based MPSoCs. In: 17th IFIP/IEEE International Conference on Very Large Scale Integration, 2009, Florian�polis. VLSI-SoC, 2009. Paper 49, 6p.

CARARA, Everton Alceu, Oliveira, R. P., CALAZANS, N. L. V., MORAES, F. G. HeMPS - A Framework for Noc-Based MPSoC Generation. In: IEEE International Symposium on Circuits and Systems - ISCAS'09, Taipei, 2009, pp. 1345-1348.

MELLO, Aline Vieira de, CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques. Book chapter In: VLSI-SoC: Advanced Topics on Systems on a Chip. Ed. Dordrecht: Springer, April, 2009, v.291, pp. 109-130. Edited by Ricardo REIS, Vincent MOONEY and Paul HASLER. (Contains extensions of the best papers presented at the Fifteenth International Conference on Very Large Scale Integration of System on Chip - VLSI-SoC 2007 Conference, which took place in 15-17 October 2007, in Atlanta, EUA). (ask for draft version by e-mail)

BEZERRA, Jeronimo Cunha. Verification and Prototyping of Intrachip Networks: The Hermes-TB case study. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. August 2009. 77 pages. Partial Scholarship Sponsor: CAPES. (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

PETRY, Carlos Alberto. Abstract Modeling of an MPSoC Hardware. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. February 2009. 113p. Partial Scholarship Sponsor: FINEP. (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

MARCON, C�sar Augusto Missio, MORENO, Edson Ifarraguirre, CALAZANS, Ney Laert Vilar, MORAES, Fernando Gehm. Comparison of NoC Mapping Algorithms Targeting Low Energy Consumption. IET Computers & Digital Techniques, vol. 2, no. 6. November, 2008, pp. 471-482. (ask for draft version by e-mail)

CARARA, Everton Alceu, PIGATTO, Daniel Vieira, CALAZANS, Ney Laert Vilar, MORAES, Fernando Gehm. MOTIM - an Industrial Application Using NOCs. In: 21st Symposium on Integrated Circuits and Systems - SBCCI 2008, Gramado, 2008, pp. 182-187.

TEDESCO, Leonel Pablo, CALAZANS, N. L. V., MORAES, F. G. Buffer Sizing for Multimedia Flows in Packet-Switching NoCs. JICS - Journal of Integrated Circuits and Systems. vol. 3, no. 1. March, 2008, pp. 146-156.

CARARA, Everton Alceu, CALAZANS, N. L. V., MORAES, F. G. A New Router Architecture for High-Performance Intrachip Networks. JICS - Journal of Integrated Circuits and Systems. vol. 3, no. 1. March, 2008, pp. 123-131.

MORENO, Edson Ifarraguirre, POPOVICI, Katalin, CALAZANS, Ney Laert Vilar, JERRAYA, Ahmed Amine. Integrating Abstract NoC Models within MPSoC Design. In: 18th Annual IEEE/IFIP International Symposium on Rapid Systems Prototyping - RSP 2008, Monterrey, June, 2008, pp. 65-71.

GUINDANI, Guilherme Montez; REINBRECHT, Cezar; RAUPP, Thiago; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. NoC Power Estimation at the RTL Abstraction Level. In: IEEE Computer Society Annual Symposium on VLSI Design - ISVLSI 2008, Montpellier, April, 2008, pp. 475-478.

DISCONZI, Rosana Perazzolo. Modeling and Validation of Intrachip Networks through Behavioral Synthesis. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. October 2007. 145p. (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

MELLO, Aline Vieira de, CALAZANS, N. L. V., MORAES, Fernando Gehm. Rate-based Scheduling Policy for QoS Flows in Networks on Chip. In: 15th Annual IFIP International Conference on Very Large Scale Integration - IFIP VLSI-SOC 2007, Atlanta. 2007, pp. 140-145.

CARARA, Everton Alceu, CALAZANS, N. L. V., MORAES, Fernando Gehm. Router Architecture for High-Performance NoCs. In: 20th Symposium on Integrated Circuits and Systems - SBCCI 2007, Rio de Janeiro. New York: ACM Press, 2007, pp. 111-116.

TEDESCO, Leonel Pablo, MORAES, Fernando Gehm, CALAZANS, N. L. V. Buffer Sizing for QoS Flows in Wormhole Packet Switching NoCs. In: 20th Symposium on Integrated Circuits and Systems - SBCCI 2007, Rio de Janeiro. New York: ACM Press, 2007, pp. 99-104.

M�LLER, Leandro Heleno; GREHS, Ismael; CARVALHO, Ewerson Luiz de Souza; SOARES, Rafael Iankowski; CALAZANS, N. L. V.; MORAES, Fernando Gehm. A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. In: Reconfigurable Communication-centric SoCs - ReCoSoC'07, Montpellier, 2007, pp. 23-30.

MARCON, C�sar Augusto Missio, MORENO, Edson Ifarraguirre, CALAZANS, N. L. V., MORAES, Fernando Gehm. Evaluation of Algorithms for Low Energy Mapping onto NoCs. In: 20th Symposium on Circuits and Systems and Systems - ISCAS 2007, New Orleans. 2007, pp. 389-392.

SCHERER JUNIOR, Carlos Adail. Torus Topology Wormhole Intra-chip Networks-on-Chip: Design, Generation and Evaluation. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2007. 101p. Scholarship Sponsor: CNPq (PNM). (Presented and approved. Final volume in preparation. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

CARVALHO, Ewerson Luiz de Souza, CALAZANS, N. L. V., MORAES, Fernando Gehm. Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs. In: 18th IEEE/IFIP International Workshop on Rapid System Prototyping - RSP 2007, Porto Alegre. Los Alamitos, California: IEEE Computer Society Conference Publishing Services, 2007, pp. 34-40.

BASTOS, �rico Nunes Ferreira, CARARA, Everton Alceu, PIGATTO, D. V., CALAZANS, N. L. V., MORAES, Fernando Gehm. MOTIM - A Scalable Architecture for Ethernet Switches. In: IEEE Computer Society Annual Symposium on VLSI - ISVLSI 2007, Porto Alegre. Los Alamitos, California: IEEE Computer Society Conference Publishing Services, 2007, pp. 451-452.

CARVALHO, Ewerson Luiz de Souza, CALAZANS, N. L. V., MORAES, Fernando Gehm. Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. In: IEEE Computer Society Annual Symposium on VLSI - ISVLSI 2007, Porto Alegre. Los Alamitos, California: IEEE Computer Society Conference Publishing Services, 2007, pp. 459-460.

MARCON, C�sar Augusto Missio; PALMA, Jos� Carlos Sant'anna; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; SUSIN, Altamiro Amadeu; REIS, Ricardo Augusto da Luz. Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. Chapter 12, pp. 179-194. In: VLSI-SoC: From Systems to Silicon. Edited by Ricardo Augusto da Luz REIS, Adam OSSEIRAN and Hans-Joerg PFLEIDERER. Springer Book, ISBN: 978-0-387-73660-0. 2007. 344p. (ask for draft version by e-mail).

SOCCOL, Celso Marasca & ZUCOLOTTO, Giovani. A GNU Chess Implementation in a Multiprocessing Platform with Communication Architecture based on an Intrachip Network. End of Term Work. Computer Science Course - PUCRS. December 2006. 87 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

MELLO, Aline Vieira de; TEDESCO, Leonel Pablo; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Evaluation of Current Mechanisms Employed to Provide QoS in Networks on Chip. In: IEEE INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP - SoC2006, Tampere. 2006, pp. 115-118.

TEDESCO, Leonel Pablo; MELLO, Aline Vieira de; GIACOMET, Leonardo Luigi; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Application Driven Traffic Modeling for NoCs. In: 19TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2006, Ouro Preto. New York: ACM Press, 2006, pp. 62-67.

M�LLER, Leandro Heleno; GREHS, Ismael; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Reconfigurable Systems Enabled by a Network-on-Chip. In: 16TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS - FPL 2006. Madri, 2006, pp. 857-860.

BASTOS, �rico Nunes Ferreira. Mercury: An intra-chip Network with 2D Torus Topology and Adaptive Routing. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. January 2006. 148p. Scholarship Sponsor: CAPES. (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

MARCON, C�sar Augusto Missio. Models for Applications Mapping in Intrachip Communication Infra-structures. PhD Thesis, PPGC - II - UFRGS, Porto Alegre, Brazil. December 2005. 192p. Scholarship Sponsor: CAPES. (Presented and Approved. Research Advisor: Altamiro Amadeu Susin. Research Co-Advisor: Ney Laert Vilar Calazans) (In Portuguese)

MARCON, C�sar Augusto Missio; PALMA, Jos� Carlos Sant'anna; CALAZANS, Ney Laert Vilar; SUSIN, Altamiro Amadeu; REIS, Ricardo Augusto da Luz; MORAES, Fernando Gehm. Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. In: IFIP INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION, 2005, Perth. IFIP VLSI-SOC 2005. 2005.

MELLO, Aline Vieira de; TEDESCO, Leonel Pablo; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Virtual Channels in Networks on Chip: Implementation and Evaluation on Hermes NoC. In: 18TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2005. New York: ACM Press, 2005, pp. 178-183.

TEDESCO, Leonel Pablo; MELLO, Aline Vieira de; GARIBOTTI, Diego; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Traffic Generation and Performance Evaluation for Mesh-based NoCs. In: 18TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2005. New York: ACM Press, 2005, pp. 184-189.

PALMA, Jos� Carlos Sant'anna; MARCON, C�sar Augusto Missio; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; REIS, Ricardo Augusto da Luz; SUSIN, Altamiro Amadeu. Mapping Embedded Systems onto NoCs - The Traffic Effect on Dynamic Energy Estimation. In: 18TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2005. New York: ACM Press, 2005, pp. 196-201.

BASTOS, �rico Nunes Ferreira; SOCCOL, Celso; CALAZANS, Ney Laert Vilar. Design and Implementation of the MERCURY Communication Architecture: an intra-chip network with torus topology, centralized shared queues and virtual-cut-through switching mode. PPGCC-PUCRS Technical Report Series, TR050, 36p. August, 2005. (in Portuguese)

MARCON, C�sar Augusto Missio; KREUTZ, M�cio; SUSIN, Altamiro Amadeu; CALAZANS, Ney Laert Vilar. Models for Embedded Application Mapping onto NoCs: Timing Analysis. In: 16TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, 2005 - RSP 2005, Montreal. 2005, pp. 17-23.

MARCON, C�sar Augusto Missio; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; SUSIN, Altamiro Amadeu; REIS, Igor Maic�; HESSEL, Fabiano Passuelo. Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. In: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION - DATE'05, Munich. 2005, pp. 502-507.

KREUTZ, M�cio; MARCON, C�sar Augusto Missio; CARRO, Luigi, CALAZANS, Ney Laert Vilar; SUSIN, Altamiro Amadeu. Energy and Latency Evaluation of NoC Topologies. In: 2005 IEEE SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2005, Kobe. ISCAS 2005. 2005. p. 5866-5869.

MELLO, Aline Vieira de; M�LLER, Leandro Heleno; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. MultiNoC: A Multiprocessing System Enabled by a Network on Chip. In: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE'05). DATE 2005 Designers' Forum Proceedings, Munich. 2005, pp. 234-239.

OST, Luciano Copello; MELLO, Aline Vieira de; PALMA, Jos� Carlos Sant'anna; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. MAIA - A Framework for Networks on Chip Generation and Verification. In: ASIA SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2005, Beijing. ASP-DAC 2005. 2005. v. 1, p. 49-52.

CARARA, Everton Alceu; MELLO, Aline Vieira de; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Virtual Channels in Intra-chip Networks - Implementation in the Hermes Network. In: XI WORKSHOP IBERCHIP, 2005, Salvador. 2005. v. 1, p. 320-321. (In Portuguese)

MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; OST, Luciano Copello. HERMES: an Infrastructure for Low Area Overhead Packet-switching Networks on Chip. Integration The VLSI Journal, Amsterdam, vol. 38, no. 1, p. 69-93, October, 2004. (ask for draft version by e-mail)

MELLO, Aline Vieira de; OST, Luciano Copello; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Evaluation of Routing Algorithms in Mesh Based NoCs. PPGCC-PUCRS Technical Report Series, TR040, 11p. May, 2004.

MORAES, Fernando Gehm; OST, Luciano Copello; MELLO, Aline Vieira de; PALMA, Jos� Carlos Sant'anna; CALAZANS, Ney Laert Vilar. NOCGEN - A Tool for the Generation of Intra-chip Networks based on the HERMES Infra-structure. In: X WORKSHOP IBERCHIP, 2004, Cartagena. X Workshop Iberchip. 2004. (In Portuguese)

MORENO, Edson Ifarraguirre. Modeling, Description and Validation of Intra-Chip Networks at the Transaction Level. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2004. 137p. Scholarship Sponsor: CAPES. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; OST, Luciano Copello. HERMES: an Insfrastructure for Low Area Overhead Packet-switching Networks on Chip. PPGCC-PUCRS Technical Report Series, TR034, 26p. October, 2003.

MORAES, Fernando Gehm; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; OST, Luciano Copello; CALAZANS, Ney Laert Vilar. A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. In: IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2003. Darmstadt, Germany, pp. 318-323, 2003.

Computing Systems, specially MPSoCs

LOD�A, N.; NUNES, W. A.; SARTORI, M. L. L.; OST, L. C.; CALAZANS, N. L. V.; GARIBOTTI, R. F.; MARCON, C. A. M. Early Soft Error Reliability Analysis on RISC-V. IEEE Latin America Transactions, 2022. Accepted for publication, under editing.

VANCIN, P. H.; DOMINGUES, A. R. P.; PARAVISI, M.; JOHANN FILHO, S.; CALAZANS, N. L. V.; AMORY, A. M. Towards an Integrated Software Development Environment for Robotic Applications in MPSoCs with Support for Energy Estimations. In: IEEE International Symposium on Circuits and Systems (ISCAS'20), Sevilha. 2020. Accepted for pubblication, to be presented.

BORTOLON, F.; GIBILUKA, M.; JOHANN FILHO, S.; BAMPI, S.; CALAZANS, N. L. V.; HESSEL, F. P.; MOREIRA, M. T. Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling Applications. In: Symposium on Integrated Circuits and Systems Design (SBCCI), 2016.

JOHANN FILHO, S., MOREIRA, M. T., HECK, L. S., CALAZANS, N. L. V., HESSEL, F. P. A Processor for IoT Applications: An assessment of design space and trade-offs. Microprocessors and Microsystems, 42, pp. 156-164, May 2016.

JOHANN FILHO, S., MOREIRA, M. T., CALAZANS, N. L. V., HESSEL, F. P. The HF-RISC Processor: Performance Assessment. In: VII IEEE Latin American Symposium on Circuits and Systems, Florian�polis (LASCAS), Feb.-Mar. 2016, pp. 95-98.

PEREZ, T. D., CALAZANS, N. L. V., DE ROSE, C. A. F. System-level Impacts of Persistent Main Memory Using a Search Engine. Microelectronics Journal (ISSN: 0959-8324), 45(2), February, 2014, pp. 211-216.

AMORY, A. M.; MOREIRA, M. T.; CALAZANS, N. L. V.; MORAES, F. G.; LAZZARI, C.; LUBASZEWSKI, M. S. Evaluating the Scalability of Test Buses. In: International Symposium on System-on-Chip (SOC), 2013, Tampere, 2013. 6p.

PETRY, C. A., WACHTER, E., CASTILHOS, G. M., MORAES, F. G., CALAZANS, N. L. V. A Spectrum of MPSoC Models for Design and Verification Space Exploration. In: 23rd IEEE International Symposium on Rapid System Prototyping (RSP'12), Tampere, 2012, pp. 30-35.

ROSA, T. R. da, LARREA, V., CALAZANS, N. L. V., MORAES, F. G. Power Consumption Reduction in MPSoCs through DFS. In: 25th Symposium on Integrated Circuit and Systems Design, SBCCI'12, 2012. 6p.

PEREZ, T. D.; CALAZANS, N. L. V.; DE ROSE, C. A. F. A Preliminary Study on System-level Impact of Persistent Main Memory. In: International Symposium on Quality Electronic Design, Santa Clara (ISQED'12), 2012, pp. 85-90.

CARVALHO, Ewerson Luiz de Souza; CALAZANS, N. L. V.; MORAES, F. G. Dynamic Task Mapping for MPSoCs. IEEE Design & Test of Computers, 27(5), 2010. pp. 26-35.

RODOLFO, Taciano Ares. An Exploration of the Design Space for Processors with Floating Point Point Hardware in FPGAs. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2010. 109p. Scholarship Sponsor: CNPq (PNM). (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

RODOLFO, Taciano Ares; CALAZANS, N. L. V.; MORAES, F. G. Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. In: 2009 International Conference on Reconfigurable Computing and FPGAs (Reconfig'09), 2009, pp. 24-29.

CARUSO, Luͭs Carlos Mieres; GUINDANI, Guilherme Montex; SCHMITT, Hugo Artur Weber; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Sea of Processors Architecture for Network Intrusion Detection. In: XI WORKSHOP IBERCHIP, 2005, Salvador. 2005. v. 1, p. 247-250. (In Portuguese)

MORENO, Edson Ifarraguirre; RODOLFO, Taciano Ares; CALAZANS, Ney Laert Vilar. SoC Modeling and Description at Different Abstraction Levels. In: X WORKSHOP IBERCHIP, 2004, Cartagena. X Workshop Iberchip. 2004. (In Portuguese)

CALAZANS, Ney Laert Vilar; MORENO, Edson; HESSEL, Fabiano; ROSA, Vitor, MORAES, Fernando Gehm; CARARA, Everton. From VHDL Register Transfer Level to SystemC Transaction Level Modeling: a comparative case study. In: 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI'2003. Los Alamitos: IEEE Computer Society Press. S�o Paulo, Brazil, pp. 355-360, 2003.

MARCON, C�sar Augusto Missio; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; RIES, Luͭs Henrique Leal; HESSEL, Fabiano Passuelo. Modeling and Description of Computing Systems: a case study comparing VHDL and SDL languages. In: VIII WORKSHOP IBERCHIP. Guadalajara, Mexico. 2002. (in Portuguese)

MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MARCON, C�sar Augusto Missio; MELLO, Aline Vieira de. A Compiling and Simulation Environment for Parameterizable Embedded Processors. In: VII WORKSHOP IBERCHIP, IWS'2001. Montevid�u, Uruguay. 2001. (in Portuguese)

MORAES, Fernando Gehm; MELLO, Aline Vieira de; CALAZANS, Ney Laert Vilar. Embedded Processor Development Environment for Codesign Applications. In: SEMIŃRIO DE COMPUTA��O RECONFIGUŔVEL, SCR'2001.Belo Horizonte, Brazil. 2001. (in Portuguese)

Reconfigurable Systems

LUCAS, C., CORREA, D., CARDOSO, D., MAGNAGUAGNO, M., MOREIRA, M. T., CALAZANS, N. L. V., MORAES, F. G. A Generic FPGA Emulation Framework. In: IEEE International Conference on Electronics, Circuits, and Systems (ICECS'12), Sevilha, 2012, pp. 233-236.

MOHR, Adilson Arthur. PMEMD-HW: Molecular Dynamics Simulation Using Reconfigurable Hardware. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2010. 98p. Scholarship Sponsor: CNPq (PNM). (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

M�LLER, Leandro Heleno; GREHS, Ismael; CARVALHO, Ewerson Luiz de Souza; SOARES, Rafael Iankowski; CALAZANS, Ney; MORAES, F. G. A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. Dynamic Reconfigurable Network-on-chip Design: Innovation for Computational Processing and Communication. Hershey, PA: IGI Global, 2009, pp. 1-27.

LOMNE, Victor, ORDAS, Thomas, MAURINE, Philippe, TORRES, Lionel, ROBERT, Michel, SOARES, Rafael Iankowski, CALAZANS, Ney Laert Vilar. Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA. In: DESIGN, AUTOMATION AND TEST IN EUROPE - DATE'09, Nice, 2009, pp. 634-639.

LOMNE, Victor, ORDAS, Thomas, MAURINE, Philippe, TORRES, Lionel, ROBERT, Michel, SOARES, Rafael Iankowski, CALAZANS, Ney Laert Vilar. Triple Rail Logic Robustness against DPA. In: 2008 International Conference on Reconfigurable Computing and FPGAs. ReConFig 2008, Cancun, 2008.

M�LLER, Leandro Heleno; SOARES, Rafael Iankowski; CARVALHO, Ewerson Luiz de Souza; GREHS, Ismael; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Infrastructure for Dynamic Reconfigurable Systems: Choices and Trade-offs. In: 19TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2006, Ouro Preto. 2006, pp. 44-49.

SOARES, Rafael Iankowski. Reconfigurable Hardware Configuration Control in Software: Infrastructure and Implementation. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. January 2006. 145p. Scholarship Sponsor: CAPES. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese).

MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; M�LLER, Leandro Heleno; BRI�O, Eduardo Wenzel, CARVALHO, Ewerson Luiz de Souza. Dynamic and Partial Reconfiguration in FPGA SoCs: Requirements and Tools. Chapter 13, pp. 157-168. In: New Algorithms, Architectures and Applications for Reconfigurable Computing. Edited by Patrick LYSAGHT & Wolfgang ROSENSTIEL. Springer Book, ISBN: 1-4020-3127-0, 2005. 313p. (ask for draft version by e-mail)

M�LLER, Leandro Heleno; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Reconfigurable Processors: State of the Art. In: XI WORKSHOP IBERCHIP, 2005, Salvador. 2005. p. 110-113. (In Portuguese)

CARVALHO, Ewerson Luiz de Souza; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; MESQUITA, Daniel. Reconfiguration Control for Dynamically Reconfigurable Systems. In: XIX CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS, 2004, Bordeaux. DCIS'2004. 2004, pp. 405-410.

CARVALHO, Ewerson Luiz de Souza; CALAZANS, Ney Laert Vilar; BRI�O, Eduardo Wenzel; MORAES, Fernando Gehm. PADReH - A Framework for the Design and Implementation of Dynamically and Partially Reconfigurable Systems. In: 17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI 2004, 2004, Ipojuca. 17th Symposium on Integrated Circuits and Systems Design - SBCCI 2004. New York: ACM Press, 2004, pp. 10-15.

M�LLER, Leandro Heleno; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; BRI�O, Eduardo Wenzel; CARVALHO, Ewerson Luiz de Souza; CAMOZZATO, Daniel. FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. In: FPL - THE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2004, Antwerp, Belgium. FPL'04. Berlin: Springer-Verlag, 2004, pp. 1042-1046.

PALMA, J. C. S.; MELLO, A. V.; MÖLLER, L. H.; MORAES, F. G.; CALAZANS, N. L. V. Core Communication Interface for FPGAs. JICS - Journal of Integrated Circuits and Systems, 1(1) Mar. 2004.

CARVALHO, Ewerson Luiz de Souza; M�LLER, Frederico Bartz; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Design Frameworks and Configuration Controllers for Dynamic and Partial Reconfiguration. PPGCC-PUCRS Technical Report Series, TR042, 17p. June, 2004.

CARVALHO, Ewerson Luiz de Souza; M�LLER, Frederico Bartz; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Configuration Control in Dynamically and Partially Reconfigurable Systems. In: X WORKSHOP IBERCHIP, 2004, Cartagena. X Workshop Iberchip. 2004. (In Portuguese)

BRIÃƒO, Eduardo Wenzel; CAMOZZATO, Daniel; RIES, Luͭs Henrique Leal; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Partial and Dynamic Reconfiguration of Intellectual Property Cores with Standardized Communication Interfaces. In: X WORKSHOP IBERCHIP, 2004, Cartagena. X Workshop Iberchip. 2004. (In Portuguese)

CARVALHO, Ewerson Luiz de Souza. RSCM - A Configuration Controller for Reconfigurable Hardware Systems. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2004. 155p. Scholarship Sponsor: CNPq. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

BRIÃƒO, Eduardo Wenzel. Dinamyc and Partial Reconfiguration for Intellectual Property Cores. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. January 2004. 149p. Scholarship Sponsor: CNPq. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans). (In Portuguese)

M�LLER, Leandro Heleno; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Tools for Partial, Remote and Dynamic Reconfiguration of Virtex FPGAs. PPGCC-PUCRS Technical Report Series, TR035, 29p. November, 2003. (in Portuguese)

CALAZANS, Ney Laert Vilar; BRIÃO, Eduardo Wenzel. Tutorials on Partial and Dynamic Reconfiguration using the Modular Design Design Flow on the Insight V2MB100 Platform. PPGCC-PUCRS Technical Report Series, TR033, 93p. October, 2003. (in Portuguese)

MESQUITA, Daniel; MORAES, Fernando Gehm; PALMA, Jos� Carlos Sant'anna; M�LLER, Leandro Heleno; CALAZANS, Ney Laert Vilar. Remote and Partial Reconfiguration of FPGAs: tools and trends. In: 10TH RECONFIGURABLE ARCHITECTURES WORKSHOP, RAW'03. Nice, France. 2003.

MESQUITA, Daniel; MORAES, Fernando Gehm; PALMA, Jos� Carlos Sant'anna; M�LLER, Leandro Heleno; CALAZANS, Ney Laert Vilar. Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. In: Design, Automation and Test in Europe Conference and Exhibition, DATE'03. Munich, Germany, pp. 1122-1123. 2003.

PALMA, Jos� Carlos Sant'anna; MELLO, Aline Vieira de; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Core Communication Interface for FPGAs. In: 15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI'2002. Los Alamitos: IEEE Computer Society Press. Porto Alegre, Brazil. 2002.

PALMA, Jos� Carlos Sant'anna; MELLO, Aline Vieira de; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Core Communication Interface in FPGAs. In: VIII WORKSHOP IBERCHIP. Guadalajara, Mexico. 2002. (in Portuguese)

MESQUITA, Daniel; MORAES, Fernando Gehm; PALMA, Jos� Carlos Sant'anna; M�LLER, Leandro; CALAZANS, Ney Laert Vilar. Partial and Remote Core Reconfiguration in FPGAs. In: VII WORKSHOP IBERCHIP, IWS'2001. Montevid�u, Uruguay. 2001. (in Portuguese)

MESQUITA, Daniel; MORAES, Fernando Gehm; M�LLER, Leandro; CALAZANS, Ney Laert Vilar. Remote and Partial Reconfiguration of Virtex Family FPGA Devices. In: SEMIŃRIO DE COMPUTA��O RECONFIGUŔVEL, SCR'2001.Belo Horizonte, Brazil. 2001. (in Portuguese)

SARMENTO, Marcelo. Self-Reconfigurable Architectures in Digital Systems. End of Term Work. Computer Science - PUCRS. June 2001. 101 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

Fast Prototyping of Digital Systems

FERREIRA, Bruno Fin. Elliptic Curve Cryptography in Hardware for Secure Systems: A Multi-Use Reconfigurable Soft IP. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2014. Scholarship Sponsor: CNPq (PNM). (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans).

FERREIRA, B. F., CALAZANS, N. L. V. A Flexible Soft IP Core for Standard Implementations of Elliptic Curve Cryptography in Hardware. In: 2013 IEEE International Conference on Electronics, Circuits, and Systems (ICECS'13), Dubai, 2013, pp.577-580.

RODOLFO, Taciano Ares. An Exploration of the Design Space for Processors with Floating Point Point Hardware in FPGAs. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. March 2010. 109p. Scholarship Sponsor: CNPq (PNM). (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

GUINDANI, G. M. ; CALAZANS, N. L. V. ; MORAES, F. G. A 10 Gbps OTN Framer Implementation Targeting FPGA Devices. In: 2009 International Conference on Reconfigurable Computing and FPGAs (Reconfig'09), 2009, pp. 30-35.

SARTIN, Maicon Aparecido. A Communication API for Hardware Acceleration of Molecular Simulators. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. July 2009. 106p. Partial Scholarship Sponsors: CAPES-FAPEMAT. (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

CARUSO, Luͭs Carlos Mieres, GUINDANI, G. M., SCHMITT, Hugo Artur Weber, CALAZANS, N. L. V., MORAES, Fernando Gehm. SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems. In: 18th IEEE/IFIP International Workshop on Rapid System Prototyping - RSP2007, Porto Alegre. Los Alamitos, California: IEEE Computer Society Conference Publishing Services, 2007, pp. 27-33.

MARCON, C�sar Augusto Missio; PALMA, Jos� Carlos Sant'anna; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Design and Prototyping of an SDH-E1 Mapper Soft-core. Revista da Sociedade Brasileira de Telecomunica��es (currently called Journal of Communication and Information Systems - JCIS, Campinas, vol 20, no. 2, p. 74-82, August, 2005.

CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; MARCON, C�sar Augusto Missio; PALMA, Jos� Carlos Sant'anna. Design, Validation and Prototyping of the EMS SDH STM-1 Mapper Soft-core. In: 6TH IEEE LATIN-AMERICAN TEST WORKSHOP, 2005, Salvador. LATW 2005. 2005. p. 313-318.

MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MARCON, C�sar Augusto Missio; MESQUITA, Daniel; PALMA, Jos� Carlos Sant'anna; BLAUTH, Victor Hugo. Design and Prototyping of an E1 Drop_Insert Soft Cores. IEE Proceedings - Communications, London, vol. 150, no. 4, pp. 239-243, August, 2003. (ask for draft version by e-mail)

MARCON, C�sar Augusto Missio; HESSEL, Fabiano Passuelo; AMORY, Alexandre Morais; RIES, Luͭs Henrique Leal; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Prototyping of Embedded Digital Systems from SDL Language: a case study. In: SEVENTH ANNUAL IEEE INTERNATIONAL WORKSHOP ON HIGH LEVEL DESIGN VALIDATION AND TEST, HLDVT'02. Cannes, France, pp. 133-138. 2002.

TOROK, Delfim Luiz. Design for Prototyping of the Medium Access Protocol in Ethernet Networks. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. August 2001. 136p. (Presented and approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; TOROK, Delfim Luiz; ANDREOLI, Andrey Vedana. Design for Prototyping of a MAC Ethernet IP soft Core. Revista de Inform�tica Te�rica e Aplicada, Porto Alegre, vol. 8, no. 1, pp. 23-41, 2001. (in Portuguese)

MORAES, Fernando Gehm; AMORY, Alexandre Morais; CALAZANS, Ney Laert Vilar; BEZERRA, Eduardo Augusto; PETRINI J�NIOR, Juracy. Using the CAN Protocol and Reconfigurable Computing Technology For Web-Based Smart House Automation. In: 14TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN - SBCCI'2001. Los Alamitos: IEEE Computer Society Press. Piren�polis, Brazil. 2001.

TOROK, Delfim Luiz; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; ANDREOLI, Andrey Vedana. Design, Implementation and Validation of an Ethernet IP Soft Core on reconfigurable Devices. In: VII WORKSHOP IBERCHIP, WS'2001, IWS'2001. Montevid�u, Uruguay. 2001 (in Portuguese)

CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; QUINTANS, Katherine Beserra; NEUWALD, Felipe Barp. Accelerating Sorting through the Use of Reconfigurable Hardware. In: Reconfigurable Computing - Experiences and Perspectives. Marͭlia, Brazil, pp. 30-35. 2000.

MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; FERREIRA, Ewerton Hofler; LIEDKE, Daniel Carvalho. Efficient Implementation of a Load/store Architecture in VHDL. In: Reconfigurable Computing - Experiences and Perspectives. Marͭlia, Brazil, pp. 2-13. 2000. (in Portuguese)

MORAES, Fernando Gehm; FERREIRA, Ewerton Hofler; CALAZANS, Ney Laert Vilar. Implementation of a Load/store Architecture in a Prototyping Environment. PPGCC-PUCRS Technical Report Series, TR002, 48p. May, 2000. (in Portuguese)

MORAES, Fernando Gehm, CALAZANS, Ney Laert Vilar, SILVA, Felipe Rocha, BARRIOS, Maur�cio. Cleo-LIRMM: An Experiment of Dedicated Processors Implementation on Embedded Systems Prototyping Platforms. In: V WORKSHOP IBERCHIP, Lima, Peru, pp.81-90.1999. (in Portuguese)

VARGAS, Fabian, MORAES, Fernando Gehm, CALAZANS, Ney Laert Vilar, BEZERRA, Eduardo Augusto. HardSoft: Reconfigurable Platform for Characterization under Radiation of Electronic Components Employed in Satellites. In: VII SIMP�SIO DE COMPUTADORES TOLERANTES A FALHAS, SCTF. Campina Grande, Brazil, pp.139-152.1997. (in Portuguese)

Telecom Digital Systems

JURACY, L. R.; LAZZAROTTO, F. B.; PIGATTO, D. V.; CALAZANS, N. L. V.; MORAES, F. G. XGT4: an Industrial Grade, Open Source Tester for Multi-Gigabit Networks. In: IEEE International Conference on Electronics, Circuits and Systems (ICECS'17), Batumi, 2017. pp. 252-255.

BONDAN, Lucas, GOBBI, Rodrigo Celso and FOCHI, Vinͭcius Morais. The Link Aggregation Protocol LACP: A simulator and the Packet Marking Protocol. End of Term Work. Computer Engineering - PUCRS. December 2011. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

OLIVEIRA, Roberto Port de. Development of an IGMP Protocol for Ethernet Switches. End of Term Work. Computer Engineering - PUCRS. December 2010. 80 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)

BASTOS, �rico Nunes Ferreira, CARARA, Everton Alceu, PIGATTO, D. V., CALAZANS, N. L. V., MORAES, Fernando Gehm. MOTIM: A Scalable Architecture for Ethernet Switches. In: IEEE Computer Society Annual Symposium on VLSI - ISVLSI 2007, Porto Alegre. Los Alamitos, California: IEEE Computer Society Conference Publishing Services, 2007, pp. 451-452.

MARCON, C�sar Augusto Missio; PALMA, Jos� Carlos Sant'anna; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Design and Prototyping of an SDH-E1 Mapper Soft-core. Revista da Sociedade Brasileira de Telecomunica�͵es (currently called Journal of Communication and Information Systems - JCIS, Campinas, vol 20, no. 2, p. 74-82, August, 2005.

CASTANHEIRA, Leonardo Dutra. Flexible Traffic Generation with Application to ATM Networks. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. February 2003. 138p. (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

SOUZA, Sheila Moreira. ATM Adaptation Layers for the Transfer of Data and Voice. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. January 2003. 151p. (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; MARCON, C�sar Augusto Missio; BLAUTH, Vitor Hugo; VALIATI, Ronaldo; MANFROI, �dison. Effective Industry-Academia Cooperation in Telecom: a method, a case study and some initial results. In: XIX SIMP�SIO BRASILEIRO DE TELECOMUNICAԡԢES, SBrT'2001. Fortaleza, Brazil. 2001.

Electronic Design Automation Tools

MOREIRA, M. T.; ARENDT, M.; ZIESEMER, A.; REIS, R.; CALAZANS, N. L. V. Automated Synthesis of Cell Libraries for Asynchronous Circuits. In: 27th Symposium on Integrated Circuits and Systems Design (SBCCI'14), 2014. pp. 183-188.

MOREIRA, M. T., ARENDT, M. E., ZIESEMER JR., A., REIS, R. A. L., CALAZANS, N. L. V. Automated Synthesis of Cell Libraries for Semi-Custom Asynchronous Design. In: International Symposium on Asynchronous Circuits and Systems (ASYNC'14-Demos), 2014. pp. 49-50.
ZIESEMER JR., A.; REIS, Ricardo Augusto da Luz; MOREIRA, M. T.; ARENDT, M. E.; CALAZANS, N. L. V. A Design Flow for Physical Synthesis of Digital Cells with ASTRAN. In: 24th Great Lakes Symposium on VLSI (GLSVLSI'14), Houston, 2014, pp. 245-246.
MOREIRA, M. T.; CALAZANS, N. L. V.; SILVA, A. N.; MARTINS, M. G. A.; REIS, A. I.; RIBAS, R. P. Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? In: International Symposium on Asynchronous Circuits and Systems (ASYNC'14), Potsdam, 2014, pp. 53-60.
ZIESEMER JR., A. ; REIS, Ricardo Augusto da Luz ; MOREIRA, M. T. ; ARENDT, M. E. ; CALAZANS, N. L. V. Automatic Layout Synthesis with ASTRAN Applied to Asynchronous Cells. In: 5th IEEE Latin American Symposium on Circuits and Systems (LASCAS'14), Santiago, February 2014, 4p.
Matheus Gibiluka. Design and Implementation of an Asynchronous NoC Router Using a Transition-Signaling Bundled-Data Protocol. End of Term Work. Computer Engineering - PUCRS, 2013. 110p. (Presented and approved. Advisor: Ney Laert Vilar Calazans)
MOREIRA, M. T., OLIVEIRA, C. H. M., Calazans, N. L. V., OST, L. C. LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries. In: 16th Euromicro Conference on Digital System Design (DSD'13), Santander, 2013.
MOREIRA, M. T., CALAZANS, N. L. V. Electrical Characterization of a C-Element with LiChEn. In: IEEE International Conference on Electronics, Circuits, and Systems (ICECS'12), Sevilha, 2012, pp. 583-585. PhD Competition Award Winner.
LUCAS, C., CORREA, D., CARDOSO, D., MAGNAGUAGNO, M., MOREIRA, M. T., CALAZANS, N. L. V., MORAES, F. G. A Generic FPGA Emulation Framework. In: IEEE International Conference on Electronics, Circuits, and Systems (ICECS'12), Sevilha, 2012, pp. 233-236.
MARCON, C. A. M.; CALAZANS, N. L. V.; MORENO, E. I.; MORAES, F. G.; HESSEL, F. P.; SUSIN, A. A. CAFES: A Framework for Intrachip Application Modeling and Communication Architecture Design. Journal of Parallel and Distributed Computing vol. 71, 2011, pp. 714-728.

MOREIRA, M. T., OLIVEIRA, B. S., PONTES, J. J. H., CALAZANS, N. L. V. A 65nm Standard Cell Set and Flow Dedicated to Automated Asynchronous Circuits Design. In: 24th IEEE International SoC Conference (SoCC'11), 2011, pp. 99-104.
SOCCOL, Celso Marasca & ZUCOLOTTO, Giovani. A GNU Chess Implementation in a Multiprocessing Platform with Communication Architecture based on an Intrachip Network. End of Term Work. Computer Science Course - PUCRS. December 2006. 87 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)
OST, Luciano Copello; MELLO, Aline Vieira de; PALMA, Jos� Carlos Sant'anna; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. MAIA - A Framework for Networks on Chip Generation and Verification. In: ASIA SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2005, Beijing. ASP-DAC 2005. 2005. v. 1, p. 49-52.
AMORY, Alexandre Morais; MORAES, Fernando Gehm; OLIVEIRA, Leandro Augusto de; CALAZANS, Ney Laert Vilar; HESSEL, Fabiano Passuelo. A Heterogeneous and Distributed Co-Simulation Environment. In: 15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI'2002. Los Alamitos: IEEE Computer Society Press. Porto Alegre, Brazil. 2002.
AMORY, Alexandre Morais; MORAES, Fernando Gehm; OLIVEIRA, Leandro Augusto de; HESSEL, Fabiano Passuelo; CALAZANS, Ney Laert Vilar. Development of a Distributed and Heterogeneous Cossimulation Environment. In: VIII WORKSHOP IBERCHIP. Guadalajara, Mexico. 2002. (in Portuguese)
MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MARCON, C�sar Augusto Missio; MELLO, Aline Vieira de. A Compiling and Simulation Environment for Parameterizable Embedded Processors. In: VII WORKSHOP IBERCHIP, IWS'2001. Montevid�u, Uruguay. 2001. (in Portuguese)
PALMA, Jos� Carlos Sant'anna; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Methods for Development and Distribution of IP Cores. In: SEMIŃRIO DE COMPUTA��O RECONFIGUŔVEL, SCR'2001.Belo Horizonte, Brazil. 2001. (in Portuguese)
MARQUES, Paulo C�sar, MORAES, Fernando Gehm, CALAZANS, Ney Laert Vilar. PMAZE: Modeling and Routing for FPGAs. In: V WORKSHOP IBERCHIP, Lima, Peru, pp.70-80.1999. (in Portuguese)
CALAZANS, Ney Laert Vilar. Automated Logic Design of Sequential Digital Circuits. Rio de Janeiro: Imprinta Gr�fica e Editora Ltda - UFRJ. 342p. 1998. (Book published in the context of the 11th. Computing School, realized from 20-24 July 1998) (Courses Slides also available) (In Portuguese)
MADEIRA, Andr� Duque. Graph Coloring: theory and applications to VLSI synthesis. End of Term Work. Computer Science - PUCRS. December 1998. 101 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)
CALAZANS, Ney Laert Vilar, MADEIRA, Andr� Duque. ASSTUCE - An exploratory Environment for Finite State Machines. In: XXIII CONFERENCIA LATINOAMERICANA DE INFORḾTICA, CLEI, Valparaiso, Chile. v.1, pp.117-126.1997.
CARDOSO, Luciano Barbosa. COFECO: A Set of Tools for Integrated Hardware and Software Design. End of Term Work. Computer Science - PUCRS. 1997. 47 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)
VENCATO, F�bio Clever. XAsstuce: A Graphic and Textual Interface for the Asstuce Exploratory Environment of Finite State Machines. End of Term Work. Computer Science - PUCRS. 1996. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)
SAURESSIG, Guilherme. MEMCE: An Algorithm for State Minimization in the Asstuce Environment. End of Term Work. Computer Science - PUCRS. 1996. 133 p. (Presented and approved. Advisor: Ney Laert Vilar Calazans) (In Portuguese)
CALAZANS, Ney Laert Vilar. Considering State Minimization during State Assignment. In: I IBERO AMERICAN MICROELECTRONICS CONFERENCE - X CONGRESS OF THE BRAZILIAN MICROELECTRONICS SOCIETY, Canela, RS, pp.49-58. 1995.
CALAZANS, Ney Laert Vilar. Methods and Tools for the Design of Digital Systems. In: III ESCOLA REGIONAL DE INFORḾTICA - ERI, Caxias do Sul, Brazil. 1995, pp.34-53. Text of Invited Short Course. (in Portuguese)
CALAZANS, Ney Laert Vilar. Boolean Constrained Encoding: a new formulation and a case study. In: INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - ICCAD'94, San Jose, CA, pp.702-706. 1994.
CALAZANS, Ney Laert Vilar. State Minimization and State Assignment of Finite State Machines: their relationship and their impact on the implementation. PhD Thesis, Université Catholique de Louvain - UCL, Louvain-la-Neuve, Belgium. October 1993.
CALAZANS, Ney Laert Vilar, ZHANG, Qinhai, JACOBI, Ricardo Pezzuol, YERNAUX, Bruno, TRULLEMANS, Anne Marie. Advanced Ordering and Manipulation Techniques for Binary Decision Diagrams. In: EUROPEAN CONFERENCE ON DESIGN AUTOMATION, EDAC'92. Brussels, Belgium, pp.452-457. 1992.
CALAZANS, Ney Laert Vilar. State Minimization and State Assignment of Finite State Machines. their relationship and their impact on the implementation. In: IFIP INTERNATIONAL WORKSHOP ON APPLICATION-ORIENTED SYNTHESIS. Dresden, Germany. 1992.
CALAZANS, Ney Laert Vilar, JACOBI, Ricardo Pezzuol, ZHANG, Qinhai, TRULLEMANS, Charles. Improving BDDs manipulation through incremental reduction and enhanced heuristics. In: CUSTOM INTEGRATED CIRCUITS CONFERENCE, CICC'91. San Diego, CA, pp.1131-1135. 1991. (Presentation Slides)
JACOBI, Ricardo Pezzuol, CALAZANS, Ney Laert Vilar, TRULLEMANS, Charles. Incremental Reduction of Binary Decision Diagrams. In: INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS'91. Singapore, Singapore, pp.3174-3177. 1991.
CALAZANS, Ney Laert Vilar, WEBER, Taisy da Silva. Logic Minimization for Combinational Circuits. In: IV SIMP�SIO BRASILEIRO DE CONCEP��O DE CIRCUITOS INTEGRADOS, SBCCI. Rio de Janeiro, Brazil, pp.52-61. 1989. (in Portuguese)
CALAZANS, Ney Laert Vilar. CIPREDI: Initial Contribution to a Design Method for Pre-Diffused Integrated Circuits. MSc Dissertation, Universidade Federal do Rio Grande do Sul - UFRGS, CPGCC, Porto Alegre, RS, Brazil. October, 1988. (in Portuguese)
CALAZANS, Ney Laert Vilar, REY, Leandro Fortes, WAGNER, Fl�vio Rech. A Logic Simulator for an Integrated Environment of Digital Hardware Design. In: III CONGRESSO DA SOCIEDADE BRASILEIRA DE MICROELETRԝNICA, SBMICRO. S�o Paulo, Brazil, pp.385-395. 1988.
CALAZANS, Ney Laert Vilar. Specification of EDGAR - A Mask Editor for Gate Array Integrated Circuits. In: XIV SEMIŃRIO INTEGRADO DE SOFTWARE E HARDWARE, SEMISH. Salvador, Brazil, pp.117-130. 1987. (in Portuguese)
CALAZANS, Ney Laert Vilar, BARONE, Dante Augusto Couto. Proposal of a New Base Cell for Pre-diffused circuits in the CIPREDI Methodology. In: II CONGRESSO DA SOCIEDADE BRASILEIRA DE MICROELETRԝNICA, SBMICRO. S�o Paulo, Brazil, pp.212-222. 1987. (in Portuguese)

Educational Resources

BEZERRA, Eduardo Augusto; POUCHET, Marianne; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; GOUGH, Michael. An Adaptable Educational Platform for Engineering and IT Laboratory Based Courses. In: 2002 FRONTIERS IN EDUCATION CONFERENCE, FIE'02. Boston, MA. 2002.

CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; MARCON, C�sar Augusto Missio. Teaching Computer Organization and Architecture with Hands-on Experience. In: 2002 FRONTIERS IN EDUCATION CONFERENCE, FIE'02. Boston, MA. 2002.

MORAES, Fernando Gehm; ZORZO, Avelino Francisco; CALAZANS, Ney Laert Vilar. Deriving Different Computer Science Curricula from a Common Core of Disciplines. In: INFORMATICS CURRICULA, TEACHING METHODS AND BEST PRACTICE, ICTEM'2002. Florian�polis, Brazil, pp. 43-49. 2002.

CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Integrating the Teaching of Computer Organization and Architecture with Digital Hardware Design Early in Undergraduate Courses. IEEE Transactions on Education, Piscataway, vol. 44, no. 2, pp. 109-119, 2001. May, 2001. (ask for draft version by e-mail)

BEZERRA, Eduardo Augusto; POUCHET, Marianne; STIPIDIS, Elias; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; EINSFELDT, Augusto. RECKON - A reconfigurable prototyping kit for engineering and IT laboratory based courses. In: SEMIŃRIO DE COMPUTA��O RECONFIGUŔVEL, SCR'2001.Belo Horizonte, Brazil. 2001.

CALAZANS, Ney Laert Vilar, MORAES, Fernando Gehm. VLSI Hardware Design by Computer Science Students: How early can they start? How far can they go?. In: 1999 FRONTIERS IN EDUCATION CONFERENCE, San Juan. IEEE Computer Society Press, pp.13612-13617. 1999.

Applications and Other Subjects

MOREIRA, L. C.; VICTOR, M. H.; SAOTOME, O.; HECK, G.; CALAZANS, N. L. V.; MORAES, F. G. A differential IR-UWB transmitter using PAM modulation with adaptive PSD. Analog Integrated Circuits and Signal Processing, 106(1), January 2021. pp.339-350.

MOREIRA, L. C.; FONTEBASSO NETO, J.; OLIVEIRA, W. S.; FERAUCHE, T.; HECK, G.; CALAZANS, N. L. V.; MORAES, F. G. An IR-UWB pulse generator using PAM modulation with adaptive PSD in 130nm CMOS process. In: 32nd Symposium on Integrated Circuits and Systems Design (SBCCI'19), S�o Paulo, 2019. 6p.

BENFICA, J., POEHLS, L. B., VARGAS, Fabian Luis, LIPOVETZKY, J., LUTENBERG, A., GARC͍A, S., GATTI, E., HERNANDEZ, F., CALAZANS, N. Configurable Platform for IC Combined Tests of Total-Ionizing Dose Radiation and Electromagnetic Immunity. In: IEEE Latin-American Test Workshop (LATW'11), March 2011.

BENFICA, J.; BOLZANI POEHLS, L. M.; VARGAS, F.; LIPOVETZKY, J.; LUTENBERG, A.; GARCIA, S. E.; GATTI, E.; HERNANDEZ, F.; CALAZANS, N. L. V. Evaluating the use of a Platform for combined Tests of Total Ionizing Dose Radiation and Electromagnetic Immunity. In: 12th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sevilla, 2011. p.473-478.

LOMNE, V., DEHBAOUI, A., ORDAS, Thomas, MAURINE, P., TORRES, Lionel, ROBERT, Michel, SOARES, Rafael Iankowski, CALAZANS, N. L. V., MORAES, F. G. Secure Triple Track Logic Robustness against Differential Power and Electromagnetic Analyses. JICS - Journal of Integrated Circuits and Systems, vol. 4, no.1, 2009, pp. 20-28.

CAPPELATTI, E. A, MORAES, F. G., CALAZANS, N. L. V., OLIVEIRA, L. H. A. High Performance Bus for Software-Hardware Interaction. Revista Tecnologia e Tend�ncias, 3(1), p.7 - 18, 2004. (In Portuguese)

MARCON, C�sar Augusto Missio; AMORY, Alexandre Morais; LUBASZEWSKI, Marcelo Soares; SUSIN, Altamiro Amadeu; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; HESSEL, Fabiano Passuelo. Applying Memory Test to Embedded Systems. In: 5TH IEEE LATIN-AMERICAN TEST WORKSHOP, 2004, Cartagena. LATW 2004. 2004.

CALAZANS, Ney Laert Vilar; IDE, Alessandro Noriaki; MORENO, Edson Ifarraguirre; RODOLFO, Taciano Ares; MORAES, Fernando Gehm. Tutorial and Directives for Design Capture, Validation and Prototyping of Hardware Modules Described in SystemC. PPGCC-PUCRS Technical Report Series, TR036, 48p. November, 2003. (in Portuguese)

MARCON, C�sar Augusto Missio; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Requirements, Primitives and Models for Systems Specification. In: 15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI'2002. Los Alamitos: IEEE Computer Society Press. Porto Alegre, Brazil. 2002.

CAPPELATTI, Ewerton Artur; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; OLIVEIRA, Leandro Augusto de. High Performance Bus for Hardware/Software Interaction. In: VII WORKSHOP IBERCHIP IWS'2001, IWS'2001. Montevid�u, Uruguay. 2001. (in Portuguese)

PALMA, Jos� Carlos Sant'anna; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Methods for Development and Distribution of IP Cores. In: SEMIN�RIO DE COMPUTA��O RECONFIGUŔVEL, SCR'2001.Belo Horizonte, Brazil. 2001. (in Portuguese)

CARNEIRO, Mára Lúcia Fernandes. Automated Synthesis of Distillation Columns: an alternative approach to the design process. MSc Dissertation, PPGCC - FACIN - PUCRS, Porto Alegre, Brazil. September 1996. 107p. (Presented and Approved. Research Advisor: Ney Laert Vilar Calazans) (In Portuguese)

CARNEIRO, M�ra L�cia Fernandes, CALAZANS, Ney Laert Vilar. Automated Design of Distillation Columns based on Probabilistic Optimization. In: XI CONGRESSO BRASILEIRO DE ENGENHARIA QU͍MICA, COBEQ. Rio de Janeiro, Brazil. 1996. (in Portuguese)

VARGAS, Fabian, VELAZCO, Raoul, AMARAL, Jos� Nelson, CALAZANS, Ney Laert Vilar, RODRIGUES, Alderico. Radiation effects on electronics: the need for ground tests. In: IX SIMP�SIO BRASILEIRO DE CONCEP��O DE CIRCUITOS INTEGRADOS - SBCCI'96. Recife. Brazil. pp.105-116. 1996.

CALAZANS, Ney Laert Vilar, BIER, Paulo Juvenal. Microphotographical Analysis of the Internal Architecture of the ADM Controller AMD9517. In: XI SEMINÁRIO INTEGRADO DE SOFTWARE E HARDWARE, SEMISH. Viçosa, Brazil, pp.149-160. 1984. (in Portuguese)

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