---------------------------------------------------------------------------------------------------
--
-- Title       : Test Bench for div_serial
-- Design      : div_serial
-- Author      : CPD
-- Company     : PUCRS
--
---------------------------------------------------------------------------------------------------
--
-- File        : $DSN\src\TestBench\div_serial_TB.vhd
-- Generated   : 11/11/2004, 11:46
-- From        : $DSN\src\divisao_serial.vhd
-- By          : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
---------------------------------------------------------------------------------------------------
--
-- Description : Automatically generated Test Bench for div_serial_tb
--
---------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity div_serial_tb is
	-- Generic declarations of the tested unit
		generic(
		size : INTEGER := 8 );
end div_serial_tb;

architecture TB_ARCHITECTURE of div_serial_tb is
	-- Component declaration of the tested unit
	component div_serial
		generic(
		size : INTEGER := 8 );
	port(
		clock : in std_logic;
		ini_div : in std_logic;
		Dendo : in std_logic_vector((size-1) downto 0);
		Dsor : in std_logic_vector((size-1) downto 0);
		fim_div : out std_logic;
		quociente : out std_logic_vector((size-1) downto 0);
		resto : out std_logic_vector((size-1) downto 0) );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal clock : std_logic;
	signal ini_div : std_logic;
	signal Dendo : std_logic_vector((size-1) downto 0);
	signal Dsor : std_logic_vector((size-1) downto 0);
	-- Observed signals - signals mapped to the output ports of tested entity
	signal fim_div : std_logic;
	signal quociente : std_logic_vector((size-1) downto 0);
	signal resto : std_logic_vector((size-1) downto 0);

  type rom is array (0 to 9) of std_logic_vector(15 downto 0);
  constant dados1 : rom :=        
  ( "1101101100110001", "0001110001110000",  "1111111111111111",
    "1111101011100001", "0000000111000110",  "0000111111111110", 
    "1100111101100100", "0000001111001001",  "0000000000000000", "1001000111001000"
  );
  
  constant dados2 : rom :=        
  ( "0001100000100001", "0000000000110001",  "1111111111111111",
    "0001100001110100", "0011000001110110",  "1111000000000110", 
    "0100000011010110", "1111001000001001",  "0000000000000000", "1001000001111000"
  ); 


begin

	-- Unit Under Test port map
	UUT : div_serial
		generic map (
			size => size
		)

		port map (
			clock => clock,
			ini_div => ini_div,
			Dendo => Dendo,
			Dsor => Dsor,
			fim_div => fim_div,
			quociente => quociente,
			resto => resto
		);

   --- gera o clock 
   process
        begin
          clock <= '0' , '1' after 5 ns;
          wait for 10 ns;
   end process;
      

   process
     variable i: integer := 0;
   begin
      ini_div <= '0';
      wait for 3 ns;
      Dendo <= dados1(i)(7 downto 0);
      Dsor <= dados2(i)(7 downto 0);
      ini_div <= '1';
      i := i + 1;
      if i=10 then i:=0; end if;
      wait for 13 ns;  -- irregular
      ini_div <= '0';
     -- wait until endop='1';  
      wait for 340 ns;
    end process;   

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_div_serial of div_serial_tb is
	for TB_ARCHITECTURE
		for UUT : div_serial
			use entity work.div_serial(div_serial);
		end for;
	end for;
end TESTBENCH_FOR_div_serial;