LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
ENTITY tb_sumNBits IS
END tb_sumNBits;
 
ARCHITECTURE behavior OF tb_sumNBits IS  

   --Inputs
   signal a : std_logic_vector(7 downto 0) := (others=>'0');
   signal b : std_logic_vector(7 downto 0) := (others=>'0');
 	--Outputs
   signal s : std_logic_vector(7 downto 0);
   signal cout : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: entity work.sumNBits 
           GENERIC MAP(nbits => 8)
           PORT MAP (a => a, b => b, cin => '0', s => s, cout => cout);
	
	a<= a+1 after 5 ns;
	b<= b+1 after 5*16 ns;

END;