Created: March, 2007
Last Update: February, 2019

Computer Engineering Undergraduate courses:

1. Microelectronics  (60-hour course) Introduction to MOS technology. MOS transistor theory. CMOS fabrication process. Electrical simulation. Basic cell design. Standard-cell design flow. Post-layout simulation. Students use Cadence products to learn Digital IC design and Verification.
   Layout tutorial (in Portuguese)
   Basic Standard Cell tutorial (in Portuguese)
2. VLSI  (60-hour course) CAD tools. Main algorithms of CAD tools. Design techniques. Design of a VLSI circuit, from VHDL to layout. Students use Cadence products to design and verify the VLSI circuit.
3. VLSI Design II  (60-hour course) Introduction to system level design techniques. Hardware-software codesign. Test of VLSI circuits (the IC is sent to the foundry in the previous course, and tested in this one).
4. Test and systems reliability  (60-hour course) Introduction to hardware and software test. DFT - design for testability and BIST - Buit in self test. Redundancy techniques (TMR).

Computer Science Graduate courses:

1. VLSI Design  (30-hour course) Introduction to MOS technology. MOS transistor theory. CMOS fabrication process. Electrical simulation. Basic cell design. Standard-cell design flow. Post-layout simulation. Students use Cadence products to learn Digital IC and Custom IC design and verification.
2. Digital and Embedded Systems   (30-hour course)Introduction to embedded systems and embedded system design. High-level specification of software and hardware of embedded systems. Verification of complex systems. Code coverage. Assertion based verification.
3. Non-synchronous Digital Circuits and  Systems  (30-hour course) Introduction to synchronous and asynchronous circuits and systems. Synchronization problems in digital systems. Asynchronous design techniques. Asynchronous design tools.

Publications that mention the use of Cadence tools:

1. A processor for IoT applications: An assessment of design space and trade-offs
   Microprocessors and Microsystems , v. 42, p.156-164, 2016
   JOHANN FILHO, S. ; MOREIRA, M. T. ; HECK, L. S. ; CALAZANS, N. L. V. ; HESSEL, F. P.
   
2. Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling Applications
   In: SBCCI , 2016, 6p.
   BORTOLON, F. ; GIBILUKA, M. ; JOHANN FILHO, S. ; BAMPI, S. ; CALAZANS, N. L. V. ; HESSEL, F. P. ; MOREIRA, M. T.
   
3. Blade - A Timing Violation Resilient Asynchronous Template
   In: International Symposium on Asynchronous Circuits and Systems (ASYNC) , 2015
   Hand, D. , Moreira, M. T. , Huang, H. H. , Chen, D. , Butzke, F. , Li, Z. , Gibiluka, M. , Breuer, M. , Calazans, N. L. V. , Beerel, P. A.
   
4. A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies
   In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , 2015
   Singhvi, A. , Moreira, M. T. , Tadros, R. , Calazans, N. L. V. , Beerel, P. A.
   
5. SDDS-NCL design: Analysis of supply voltage scaling
   In: SBCCI , 2015
   Ricardo A. Guazzelli; Fernando G. Moraes; Ney L. V. Calazans; Matheus T. Moreira
   
6. Proposal of an Exploration of Asynchronous Circuits Templates and their Applications
   FACIN Technical Report , 2014
   M. T. Moreira and N. L. V. Calazans
   
   Technical report about a research plan for implementing an environment for the design of asynchronous circuits
   
7. Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
   In: International Symposium on Asynchronous Circuits and Systems (ASYNC) , 2014
   Matheus Moreira; Augusto Neutzling; Mayler Martins; Andr?Reis; Renato Ribas; Ney Calazans
   
8. A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design
   In: International Symposium on Asynchronous Circuits and Systems (ASYNC) , 2014
   Matheus Trevisan Moreira; Michel Evandro Arendt; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans
   
9. Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis
   In: Great Lakes Symposium on VLSI (GLSVLSI) , 2014, 6p.
   Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck; Ney Laert Vilar Calazans
   
10. Design of NCL Gates with the ASCEnD Flow
    In: LASCAS , 2013
    M. T. Moreira, C. H. M. Oliveira, R. C. Porto and N. L. V. Calazans
    
11. A 65nm standard cell set and flow dedicated to automated asynchronous circuits design
    In: SOCC , 2011, pp. 99-104.
    M. T. Moreira, B. S. Oliveira, J. J. H. Pontes, N. L. V. Calazans
    
    This work proposes a new design flow for rapid creation and characterization of standard cell sets for asynchronous design. The flow is fully automated except for the cell layout generation step. It has been applied to the design of a standard cell set supporting the Teak asynchronous synthesis tool. Cells use a 65 nm gate length commercial CMOS process. An asynchronous RSA cryptography circuit provides the design flow validation.
12. Design and Implementation of a Standard Cell Library for Building Asynchronous ASICs
    End of Term Work , Computer Engineering, PUCRS, 2011
    M. T. Moreira
    

Chip Designs:

• Design of the HF-RISC processor fabricated through Europractice - microcontroller sent for fabrication using TSMC 180 nm technology validated on silicon

   

• Design of an MBlite processor sent to MOSIS - first case study sent for fabrication at MOSIS using IBM 130 nm technology

Main Research Projects (funded by government research agencies):

• X10Giga (finished) - is a collaborative effort between PUCRS (through the GAPH Research Group), TERACOM Telemática Ltd, a Brazilian telecom equipment enterprise, the UFC (through the LESC Laboratory) and the Atlântico Institute (in Fortaleza, Ceará). The main objective of the project is to develop a transponder capable of transmitting SDH frames and Gigabit Ethernet packets over Optical Transport Networks (OTNs) with long-distance optical links. The transponder will be used as a complementary equipment or integrated within TERACOM products, aggregating functionalities that today depend on other manufacturers' equipment. The three scientific organizations (GAPH/LESC/Atlântico Institute) will contribute to develop an dominate technologies like Gigabit Ethernet (GbE) and SDH signal transport functions over OTN networks implemented in FPGAs, 10Gbps optical transceivers with integrated power amplifiers and OTN network management embedded software. The project started in March 2007 and has a duration of 36 months. It is co-financed by FINEP Brazilian research funding agency and TERACOM.
  Coordinator: Fernando Gehm Moraes
• TeTHA (finished) - is a collaborative effort between PUCRS (through the GAPH Research Group) and TERACOM Telem?ica Ltda, a Brazilian telecom equipment enterprise. The main objective of the project is to develop Intellectual Property cores (IP cores) to aid in the implementation of hardware modules for transporting Internet Protocol (IP) traffic on high speed networks that employ Ethernet in the lower layers of the communication protocol stack. The developed IP cores are to be immediately used in TERACOM products, increasing the competitivity of the enterprise in internal and world markets. The IP cores will comprise modules initially prototyped in FPGAs, followed by the generation of an IC layout mask set for ASIC fabrication. The project started in January 2006 and has a duration of 36 months.
  Coordinator: Ney Laert Vilar Calazans
• ACCUSER (ongoing) - is a collaborative effort between PUCRS (through the GAPH Research Group) and USC, University of Southern California in Los Angeles - US. The main objective of the project is to develop a new template for asynchronous circuits design using resilient architectures. To do so, specific components need to be designed at transistor level, and case studies to be synthesized targeting these components and verified through simulation and formal verification methods. To do so we employ the IC and the ETS Cadence packages for designing and characterizing basic components at the cell level. We also use the INCISIVE package for behavioral and timing simulation. The project started in November 2013 and has a duration of 36 months.
  Coordinator: Ney Laert Vilar Calazans

Contact Points: Prof. Fernando Gehm Moraes and Prof. Ney Laert Vilar Calazans

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